Arm® CoreLink™ SSE-200 Subsystem for Embedded Technical Reference Manual

Revision r1p0


Table of Contents

Preface
About this book
Product revision status
Intended audience
Using this book
Additional reading
Feedback
Feedback on this product
Feedback on content
1 Introduction
1.1 About the SSE-200
1.1.1 About IoT System on Chip implementations
1.2 Features of the SSE-200
1.3 CoreLink SIE-200 components
1.4 Compliance
1.4.1 Arm® Architecture
1.4.2 Debug
1.4.3 Interrupt controller architecture
1.4.4 Advanced Microcontroller Bus Architecture
1.5 Product revisions
2 Functional description
2.1 Top-level system partitioning
2.1.1 Overview
2.1.2 Configuration options
2.1.3 Interface signals
2.2 Clocks
2.2.1 Overview
2.2.2 Clock generation and control
2.2.3 External wakeup controller clocks
2.2.4 Power control expansion
2.2.5 Component clocks
2.3 Resets
2.3.1 Overview
2.3.2 Reset inputs and outputs
2.3.3 nPORESET handling
2.3.4 Processor reset handling
2.3.5 nWARMRESETAON
2.3.6 Power control reset
2.4 CPU elements
2.4.1 Overview
2.4.2 Cortex-M33 configurations
2.4.3 Instruction cache
2.4.4 CPU_WAIT control
2.4.5 Interrupts
2.4.6 Power domains
2.4.7 Clock domains
2.4.8 Security
2.4.9 External wakeup
2.5 Base element
2.5.1 Overview
2.5.2 Component sources
2.5.3 AHB5 bus matrix
2.5.4 SRAM
2.5.5 AHB5 TrustZone peripheral protection controllers
2.5.6 Message handling unit
2.5.7 Timers and watchdogs
2.5.8 Expansion ports
2.5.9 Security controller
2.5.10 Power control
2.6 SRAM elements
2.6.1 Overview
2.6.2 SRAM banks
2.6.3 AHB5 Exclusive Access Monitor
2.7 System control element
2.7.1 System Information Register Block
2.7.2 System Control Register Block
2.7.3 Timers and watchdogs
2.7.4 Peripheral Protection Controller
2.7.5 Power Policy Units
2.8 Debug element
2.8.1 Overview
2.8.2 Debug access
2.8.3 Timestamps
2.8.4 Cross trigger
2.8.5 CoreSight debug ROM tables
2.9 Power control infrastructure
2.9.1 Overview
2.9.2 Power domains and PPUs
2.9.3 Processor power domains
2.9.4 System boot when powering up
2.9.5 External wakeup controllers
2.9.6 Power Dependency Control Matrix
2.9.7 System and processor power states
2.9.8 Entering lower processor power states
2.9.9 Hibernation
2.9.10 Wake From Hibernation using PD_SYS power control Q-Channel interface
2.10 Crypto element
2.10.1 Persistent storage
3 Programmers Model
3.1 About the programmers model
3.2 Memory map
3.2.1 Memory map overview
3.2.2 SRAM overview
3.2.3 Processor overview
3.2.4 Base peripheral overview
3.2.5 System control overview
3.3 CPU element
3.3.1 Processor L1 cache registers
3.3.2 Processor L1 cache programming
3.3.3 Ensuring the cache handles memory modifications
3.3.4 CPU Local Security Control Register
3.3.5 CPU_IDENTITY
3.3.6 PPB regions
3.3.7 Interrupts
3.4 Base element
3.4.1 CMSDK timer
3.4.2 CMSDK dual timer
3.4.3 CMSDK watchdog timers
3.4.4 AHB5 TrustZone Memory Protection Controller
3.4.5 Message handling unit
3.4.6 Security Privilege Control Block
3.4.7 Non-secure Privilege Control Block
3.5 SRAM element
3.6 System control element
3.6.1 System control registers
3.6.2 System information registers
3.6.3 CMSDK timer
3.6.4 System Control Register block
3.6.5 Power Policy Unit registers
3.6.6 CMSDK Watchdog timer
3.7 Debug and trace
3.7.1 Debug access interface
A Signal Descriptions
A.1 Clock, reset, and power control signals
A.1.1 Functional clock and reset signals
A.1.2 Clock control Q-Channel signals
A.1.3 Power control Q-Channel signals
A.1.4 Expansion power control dependency signals
A.1.5 Power domain ON status signals
A.2 Interrupt signals
A.3 AHB expansion bus signals
A.4 Debug and Trace signals
A.4.1 DAP signals
A.4.2 Timestamp interface
A.4.3 Cross Trigger interfaces
A.4.4 Cross trigger signals
A.4.5 Debug APB expansion interface
A.4.6 ATB Trace interface
A.4.7 Debug authentication interface
A.5 Security component interfaces
A.5.1 Memory protection controller interface
A.5.2 APB peripheral protection controller interface
A.5.3 AHB peripheral protection controller interface
A.5.4 Master security expansion interface
A.5.5 Bridge buffer error interface
A.5.6 Miscellaneous security expansion signals
A.6 Miscellaneous top-level signals
A.6.1 Top-level signals
A.6.2 Top-level static configuration signals
A.7 CryptoCell-312 signals
A.7.1 CryptoCell Lifecycle Indication Interface
A.7.2 CryptoCell Debug Control Enable
A.7.3 CryptoCell Non-Volatile Memory Interface
A.8 Top-level parameters
A.9 Top-level render time configurations
B Revisions
B.1 Revisions

Release Information

Document History
Issue Date Confidentiality Change
A 20 December 2016 Confidential First release for r0p0 Beta (ARM DDI0574).
0100-00 26 September 2017 Non-Confidential First release for r1p0 EAC (ARM 101104).

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