2.9.9 Hibernation

Hibernation state is the lowest power state of the system that SSE-200 supports. When in this state, most of the system that supports power gating is turned off, except for PD_SRAM<n> in either OFF or MEM_RET, and the PD_DEBUG in either ON or OFF. In this state, normally the MAINCLK is also turned off to save power.

To enter the hibernation state, the following conditions must be met:

  • All PD_SRAM<n> domains must be configured to dynamically enter OFF or Memory Retention state.
  • Any SRAM that is expected to be used immediately after exiting hibernation, for example, for holding stack pointers, must either:

    • Have its PDCM configuration sensitivity, before entering hibernation, set to be sensitive to any of the PD_CPU<n>CORE power ON states that is associated to the core that wakes and uses that SRAM. This ensures that when the SRAM powers up after leaving hibernation, it stays powered until the associated processor turns OFF.

    • Set that SRAM lowest power state to retention so that the SRAM content is always retained even if the SRAM turns off momentarily while waiting for the processor to start accessing memory.

    This ensures that after the SRAM powers up at first assess after leaving hibernation, it stays powered until the system or its associated processor turns OFF.

  • All GPR in the debug domain are turned off, otherwise, one or more CPUs cannot power down.
  • If you have expansion logic that is interfaced to the PD_SYS power control Q-Channel interface, ensure that the expansion logic is not active and can enter a quiescent state.
  • If you have other expansion power domains in the system that are expected to stay ON or to be turned on and starting accesses when the system is still in hibernation, you must make some changes during the integration phase for the expansion region.

    You must provide gates that use the ACCWAITN signal to temporarily block access from these regions.

    You must set ACC_WAITN_RST parameter to LOW. This ensures that when the system restarts, any access from these power domains are held off until the security configurations of the system can be reinstated. After security considerations have been reinstated, Secure software can set the ACC_WAITN register flags to allow access from these power domains to proceed.

  • If the intention is to wake the system with an EWC request, all processors must enter OFF state, with at least one processor in the DEEPSLEEP WITH WIC and EWC enabled. If all cores are in the OFF state with disabled EWC, expansion logic that is able to drive the PD_SYS power control Q-Channel interface can wake the system.


The PD_SYS power domain does not take into consideration the operation state of the Timers, Watchdog timers, system controllers and the MHU that resides in PD_SYS when determining its idleness. Therefore, to prevent race conditions between the power transitioning of the system against the expansion bus access occuring, PD_SYS must be powered-up until all external interfaces are idle. Once PD_SYS has entered a lower state, all PD_SYS programmer states that occur after that, including Timer and Watchdog states and interrupts, will be lost.

The system leaves the Hibernation state when a processor is woken from the OFF state. When an EWC request is made to wake a CPU, it also requests MAINCLK to start running. After the processor has booted, and has restored the Security state, the processor must set the ACC_WAITN register to allow all other masters to access the system.

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