2.9.2 Power domains and PPUs

PPUs control all power domains in the SSE-200, except for the always on PD_AON domain.

Each PPU uses the following control signals to power the domain up or down:

  • All power Q-Channel interfaces from within the power domain.
  • Access Control Gates ACG access request into power domain.
  • The Power Dependency Control Matrix (PDCM) register settings configure all the other power dependecy control settings.
  • Debug system power up requests for the domain if they exist.

The PPU allows software to do the following:

  • Perform static power control. For example, turning the power domain permanently on or off, or putting the domain into a retention state.

    Caution:

    If software sets any key power domains, such as, PD_CPU0_CORE, or PD_SYS, to OFF or to retention, the system might not be able to power up, boot, or execute code. This can cause a system lockup, so avoid using static power control except for PD_CRYPTO domain.
  • Enable or disable dynamic power transitions and set a minimum power state. It supports a subset of the following transitions:

    • ON to OFF.
    • OFF to ON.
    • ON to RET (Memory only or Full Retention depending on the requirements of each domain).
    • RET to ON.
    • ON to Warm reset.
    • Warm reset back to ON.

Each PPU therefore uses a Q-Channel or P-Channel interface to:

  • Determine if it can bring the power domain to a required static power mode programmed by software.
  • If dynamic power transition is enabled, determine if the power domain must transition to a different power state.

In addition to internal Q-Channel and P-Channel interfaces, some power domains are able to perform power transition to ON using requests from the following:

  • The ACG at the boundary of the power domain when an access request arrives at the boundary of the domain.
  • The GPR in the debug element to power up.
  • One of the external wakeup controllers.
  • One of the power control Q-Channel expansion interface signals.

The following table lists the types of request that can wake each domain.

Table 2-12 Domains and wake-up requests

Power domain Access Control Gate GPR or DAP EWC Q-Channel expansion
PD_SYS No Yes. CPU0 GPR or CPU1 GPR. Yes. CPU0 EWC or CPU1 EWC. Yes
PD_CPU0DBG No Yes. CPU0 GPR. Yes. CPU0 EWC. No
PD_CPU0CORE No Yes. CPU0 GPR. Yes. CPU0 EWC. No
PD_CPU1DBG No Yes. CPU1 GPR Yes. CPU1 EWC. No
PD_CPU1CORE No Yes. CPU1 GPR. Yes. CPU1 EWC. No
PD_DEBUG No Yes. DAP No Yes
PD_SRAM0 Yes No No No
PD_SRAM1 Yes No No No
PD_SRAM2 Yes No No No
PD_SRAM3 Yes No No No
PD_CRYPTO No No No No

Note:

  • PD_CRYPTO only supports static power control.
  • Although wake-up of PD_SYS from OFF is supported using the PD_SYS Power Control Q-Channel interface, Arm recommends an IRQ to wake the system, especially if external ACGs use ACGWAITN output port. If an interrupt does not wake the processor, and there are no other masters able to clear the BUSWAIT.ACC_WAITN register bit to unblock access into the system, the system can deadlock. Interrupts are not required for wake from Retention.
  • PD_CPU0DBG and PD_CPU1DBG power domains do not exist if there is no support for a separate processor debug power domain.
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