2.8.1 Overview

The following figure shows a block diagram of the Debug element.

Figure 2-6 Debug element block diagram
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The Debug element provides the following features and interfaces:

In this figure, the example debug expansion logic shows an SWJ-DP being used. The SWJ-DP is a combined JTAG-DP and SW-DP that enables you to connect either an SWD or JTAG probe to a target. It is a standard CoreSight debug port.

The expansion example also shows the use of a single TPIU to bridge the ATB output to a trace output. The debug logic also provides an APB interface to allow the external debug logic to be controlled through the single DAP interface.

Note:

The default example implementation reuses the CoreSight™ SoC-400 TPIU and SWJ-DP that is provided as part of the Cortex®-M33 package. This configuration is sufficient for basic use.

For more sophisticated multiprocessor debug solution, a full CoreSight SoC IP solution can be licensed and implemented.

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