A.1.1 Functional clock and reset signals

The following table lists the clock and reset signals in the SSE-200 interfaces.

Table A-1 Clock and reset signals

Signal name Width Direction Power Domain Description
MAINCLK 1 Input AON Main Clock input. This clock is used by the system to generate most other clocks that are used within the system.
MAINCLKREQ 1 Output AON

Main Clock Request signal.

1 indicates a request for the main clock to be active.

0 indicates that the clock can be turned off.

MAINCLKRDY 1 Input AON

Main Clock Ready signal.

1 indicates that the clock is running, stable, and the system can start to use it.

0 indicates that the clock has stopped or is unstable and must not be used.

S32KCLK 1 Input AON Slow Clock. Typically, a 32KHz clock input and is asynchronous to the other clocks in the system.
nPORESET 1 Input AON Active LOW Power-on Reset Input signal.
nSRST 1 Input AON Active LOW System Reset input from Debugger.
RESETREQ 1 Input AON Active HIGH Request to perform a system reset.
EXPWARMRESETREQ 1 Output AON Active HIGH request to expansion logic to prepare for a Warm reset.
EXPWARMRESETACK 1 Input AON Active HIGH acknowledge for expansion logic to indicate that it is ready for Warm reset.
nPORESETAON 1 Output AON Active LOW System Cold reset for the Expansion System.
nWARMRESETAON 1 Output AON Active LOW System Warm reset output for the Expansion System.
FCLK 1 Output AON Ungated Fast Clock. This is generated from MAINCLK.
SYSCLK 1 Output AON Ungated System Clock. This clock is generated from FCLK and is synchronous to FCLK.
HINTSYSCLKENCLK 1 Output AON The HINTSYSCLKENCLK hint function is a clock pulse that is generated to indicate when, relative to the divided clock FCLK, an enable must be generated on SYSCLK.
EXPCLKREQ 1 Input AON

Clock Request signal from expansion hardware to request for FCLK and SYSCLK to be active.

1 indicates request for clocks to be active.

0 indicates that clocks can be turned off.

EXPCLKRDY 1 Output AON

Clock Ready signal to expansion hardware to indicate that FCLK and SYSCLK are active.

1 indicates that clocks are running, stable, and the system can start to use them.

0 indicates that clocks have stopped or are unstable and must not be used.

SYSFCLK 1 Output PD_SYS Base element Fast System Clock. This clock is to be used for Base element Expansion. This clock is synchronous to FCLK and is the PD_SYS power gated and Base element hierarchically clock gated version of FCLK.
SYSSYSCLK 1 Output PD_SYS Base element System Clock. This clock is to be used for Base element Expansion. This clock is synchronous to SYSCLK and is the PD_SYS power gated and Base element hierarchically clock gated version of SYSCLK.
SYSSYSUGCLK 1 Output AON Base element Ungated System Clock. This clock is to be used for Base element Expansion. This clock is synchronous to SYSCLK and is the PD_SYS power gated version of SYSCLK. This clock does not include Base element hierarchical clock gating. This signal is gated in the AON domain and is intended to be used only in the PD_SYS power domain.
SYSFUGCLK 1 Output AON Base element Ungated Fast Clock. This clock is for Base element expansion. It is synchronous to FCLK and is the PD_SYS power gated version of FCLK. This clock does not include Base element hierarchical clock gating. This signal is gated in the AON domain and intended to be used only in the PD_SYS power domain.
nWARMRESETSYS 1 Output PD_SYS Base element active LOW Warm Reset Output.
DEBUGFCLK 1 Output AON Debug Fast clock. This clock is to be used for Debug element Expansion only. This clock is the PD_DEBUG power gated version of FCLK and is synchronous to FCLK. This signal is gated in the AON domain and intended to be used only in the PD_DEBUG power domain.
DEBUGSYSCLK 1 Output AON Debug System clock. This clock is to be used for Debug element Expansion only. This clock is the PD_DEBUG power gated version of SYSCLK and is synchronous to SYSCLK. This signal is gated in the AON domain and intended to be used only in the PD_DEBUG power domain.
DEBUGHINTSYSCLKENCLK 1 Output AON DEBUGHINTSYSCLKENCLK is a gated version of HINTSYSCLKENCLK for the debug power domain expansion. It is a clock pulse that is generated by the divider to indicate when, relative to the divided clock DEBUGFCLK, the enable must be generated.
nPORESETDEBUG 1 Output PD_DEBUG Debug System active LOW Cold reset output. This signal is generated in the AON domain and intended to be used only in the PD_DEBUG power domain.
CRYPTOSYSCLK 1 Output PD_CRYPTO Crypto element System Clock. This clock is to be used for Crypto element Expansion. This clock is synchronous to CRYPTOSYSCLK and is the PD_CRYPTO power gated and Crypto element hierarchically clock gated version of SYSCLK. This output only exists if the Crypto element exists.
nWARMRESETCRYPTO 1 Output PD_CRYPTO

Crypto element active LOW Warm Reset output. This output only exists if the Crypto element exists.

PD_CRYPTO can be reset on Warm reset.

CPUDEBUGPIKCLK 1 Output AON CPU and Debug element Power Integration Clock. This is a hierarchically clock gated version of SYSCLK. It is intended for use by expansion power control logic that is expected to be reset using nCPUDEBUGPIKRESET, and controlled using the CPUDEBUGPIKCLK Q-Channel interface.
nCPUDEBUGPIKRESET 1 Output AON CPUDEBUGPIKCLK Reset. This reset is a CPUDEBUGPIKCLK resynchronized version of nPORESETAON reset.
BCRYPTOSPIKCLK 1 Output AON Base, Crypto, and SRAM Power Integration Clock. This is a hierarchically clock gated version of SYSCLK. It is intended for use by expansion power control logic that is expected to be reset using nBCRYPTOSPIKRESET, and controlled using the BCRYPTOSPIKCLK Q-Channel interface.
nBCRYPTOSPIKRESET 1 Output AON BCRYPTOSPIKCLK Reset. This reset is a BCRYPTOSPIKCLK resynchronized version of nWARMRESETAON reset.
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