A.8 Top-level parameters

The SSE-200 provides Verilog parameters that configure many of the SSE-200 features.

The following table lists the top-level Verilog parameters, but excludes the security control expansion, interrupt, and the Crypto element parameters.

Table A-24 Top-level parameters

Parameter Default value Description
INITNSVTOR0_RST 0x0000_0000 Sets the reset value of the Non-secure vector table offset address in the Cortex®-M33 processor, in CPU element 0.
INITNSVTOR1_RST Sets the reset value of the Non-secure vector table offset address in the Cortex-M33 processor, in CPU element 1.
SRAM_MPC_BLK_SIZE 3

SRAM MPC block size = 2SRAM_MPC_BLK_SIZE + 5 bytes:

3 = 256 byte block size.

Others = Reserved.

The block size must be consistent across different architectures because it has a major impact on the software. Different choices for the block size, increases the software porting effort.

CPU0WAIT_RST 0

For CPU element 1, controls whether the processor waits at the boot phase:

0 = Boot normally.

1 = Wait at boot.

From Cold reset, this parameter also controls if CPU 0 powers up:

0 = Power-up.

1 = Do not power up.

CPU1WAIT_RST 1

For CPU element 1, controls whether the processor waits at the boot phase:

0 = Boot normally.

1 = Wait at boot.

From Cold reset this parameter also controls if CPU 1 powers up:

0 = Power-up.

1 = Do not power up.

ACC_WAITN_RST 1

Sets the reset value of the BUSWAIT.ACC_WAITN register bit, which controls the value of the ACCWAITn output signal. This parameter can stall accesses from AHB masters until the CPU element restores security state:

1 = When exiting reset, allow AHB masters to access the AHB interconnect.

0 = When exiting reset, prevent AHB masters from accessing the AHB interconnect.

CPU0_CPUID 0x0 Sets the CPUID value in the CPU_IDENTITY register for CPU element 0.
CPU1_CPUID 0x1 Sets the CPUID value in the CPU_IDENTITY register for CPU element 1.
EXP_SYS_ID_PRESENT 0xFFFF

Each bit[n] of this vector defines whether the Exclusive Access Monitor (EAM) monitors the AHB master with HMASTERID == n. When a master is bypassed by the EAM, the EAM provides a HEXOKAY fail response but the data transfer occurs, that is, data is written to memory. This behavior might not be desirable. Therefore, Arm recommends that for masters with exclusive access capability, you must set the corresponding EXP_SYS_ID_PRESENT[n] bit to 1.

Bits[15:0] are IDs for internal use only and are not available on this interface.

SRAM0_BUFFER_ENABLE 0 When set to one, it adds buffering and a 2-cycle latency to an exclusive write access through an EAM that is associated with SRAM0. When enabled, the buffering improves the synthesis timing path through that EAM.
SRAM1_BUFFER_ENABLE 0 When set to one, it adds buffering and a 2-cycle latency to an exclusive write access through an EAM that is associated with SRAM1. When enabled, the buffering improves the synthesis timing path through that EAM.
SRAM2_BUFFER_ENABLE 0 When set to one, it adds buffering and a 2-cycle latency to an exclusive write access through an EAM that is associated with SRAM2. When enabled, the buffering improves the synthesis timing path through that EAM.
SRAM3_BUFFER_ENABLE 1 When set to one, it adds buffering and a 2-cycle latency to an exclusive write access through an EAM that is associated with SRAM3. When enabled, the buffering improves the synthesis timing path through that EAM.
CPU0_FPU 0

Indicates if the Floating Point Unit (FPU) is present in CPU element 0:

0 = FPU is not present.

1 = FPU is present.

CPU1_FPU HAS_FPU

Indicates if the FPU is present in CPU element 1:

0 = FPU is not present.

1 = FPU is present.

CPU0_DSP 0

Controls whether the Cortex-M33 processor, in CPU element 0, supports the DSP extension instructions:

0 = DSP not supported.

1 = DSP supported.

CPU1_DSP 1

Controls whether the Cortex-M33 processor, in CPU element 1, supports the DSP extension instructions:

0 = DSP not supported.

1 = DSP supported.

CPU0_CPIF 0

Controls whether CPU0 element has a coprocessor interface:

0 = Coprocessor interface is not present.

1 = Reserved.

CPU1_CPIF 0

Controls whether CPU1 element has a coprocessor interface:

0 = Coprocessor interface is not present.

1 = Reserved.

CPU0_MPU_NS 8 Sets the number of Non-secure MPU entries in CPU element 0.
CPU1_MPU_NS 8 Sets the number of Non-secure MPU entries in CPU element 1.
CPU0_MPU_S 8 Sets the number of Secure MPU entries in CPU element 0.
CPU1_MPU_S 8 Sets the number of Secure MPU entries in CPU element 1.
CPU0_SAU 8 Sets the number of SAU entries in CPU element 0.
CPU1_SAU 8 Sets the number of SAU entries in CPU element 1.
CPU0_DBGLVL 2

Sets the number of debug resources in CPU element 0:

2 = 4 watchpoint and 8 breakpoint comparators.

1 = 2 watchpoint and 4 breakpoint comparators.

CPU1_DBGLVL 2

Sets the number of debug resources in CPU element 1:

2 = 4 watchpoint and 8 breakpoint comparators.

1 = 2 watchpoint and 4 breakpoint comparators.

CPU0_ICACHESIZE 11

Sets the instruction cache size in CPU element 0:

9 = 512bytes.

10 = 1KB.

11 = 2KB.

12 = 4KB.

13 = 8KB.

14 = 16KB.

Others = Reserved.

CPU1_ICACHESIZE 11

Sets the instruction cache size in CPU element 1:

9 = 512bytes.

10 = 1KB.

11 = 2KB.

12 = 4KB.

13 = 8KB.

14 = 16KB.

Others = Reserved.

CPU0_ICACHEDMA 0

Defines the existence of micro DMA capability and also line locking capability for the CPU element 0 ICache.

CPU1_ICACHEDMA 0

Defines the existence of micro DMA capability and also line locking capability for the CPU element 1 ICache.

CPU0_ICACHESTATS 1

Controls whether the ICache supports statistics functionality in CPU element 0:

0 = Statistics not supported.

1 = Statistics supported.

CPU1_ICACHESTATS 1

Controls whether the ICache supports statistics functionality in CPU element 1:

0 = Statistics not supported.

1 = Statistics supported.

CPU0_ICACHEINVMAT 0

Enable Invalidate on Write Match for the CPU0 element ICache.

When set to 1, any writes to a location that also exists in the cache, results in the invalidation of that cache line.

CPU1_ICACHEINVMAT 0

Enable Invalidate on Write Match for the CPU1 element ICache.

When set to 1, any writes to a location that also exists in the cache, results in the invalidation of that cache line.

CPU0_XOM 0

Enable CPU0 ICache Execute Only Memory (XOM) support.

When set to 1, the HRUSER[0] signal on the AHB5 Master Expansion Code interface indicates if the current read data is Execute Only. If the data type access targets a XOM location, the ICache masks the data.

When set to 0, the ICache ignores HRUSER[0].

CPU1_XOM 0

Enable CPU1 ICache XOM support.

When set to 1, the HRUSER[0] signal on the AHB5 Master Expansion Code interface indicates if the current read data is Execute Only. If the data type access targets a XOM location, the ICache masks the data.

When set to 0, the ICache ignores HRUSER[0].

ICACHERRDS 1

Reduce ICache Tag Reads.

When set to 1, the ICache masks off an access to the Tag RAM if this set was previously accessed and the RAM data is valid.

Note:

This option requires a deselected RAM to continue outputting the last value that was read from it.
FCLKDIV_RST 15

Sets the MAINCLK to FCLK divider ratio at reset. The divider ratio is FCLKDIV_RST[4:0] + 1.

You must ensure that the default divider value does not result in an overclocked design after reset.

SYSCLKDIV_RST 0b00000

Sets the FCLK to SYSCLK divider ratio at reset. The divider ratio is SYSCLKDIV_RST[4:0] + 1.

You must ensure that the default divider value does not result in an overclocked design after reset.

FCLK_DIVRATIO_PIPELINE 2 Adds extra clock cycles, or delay cycles, to the resynchronization pipeline that passes the divider ratio values in the FCLK generation clock divider. The delay is 3 + FCLK_DIVRATIO_PIPELINE.
SYSCLK_DIVRATIO_PIPELINE 2 Adds extra clock cycles, or delay cycles, to the resynchronization pipeline that passes the divider ratio values in the SYSCLK generation clock divider. The delay is 3 + SYSCLK_DIVRATIO_PIPELINE.
SYSRSTREQ0_EN_RST 0

SYSRSTREQ0_EN reset value. SYSRSTREQ0_EN_RST controls the reset value of the SYSRSTREQ0_EN value in the RESET_MASK register. That register bit can mask the reset request from the CPU0 element.

When set to 0, at reset, CPU0 element cannot cause a system Warm reset by setting AIRCR.SYSRESETREQ = 1, in its Application Interrupt and Reset Control Register, AIRCR.

When set to 1, CPU0 element can cause a system Warm reset by setting AIRCR.SYSRESETREQ = 1.

The default value is 0, due to its interaction with the CryptoCell-312 core in the Subsystem.

SYSRSTREQ1_EN_RST 0

SYSRSTREQ1_EN reset value. SYSRSTREQ1_EN_RST controls the reset value of the SYSRSTREQ1_EN value in the RESET_MASK register. That register bit can mask the reset request from the CPU1 element.

When set to 0, at reset, CPU1 element cannot cause a system Warm reset by setting AIRCR.SYSRESETREQ = 1, in its Application Interrupt and Reset Control Register, AIRCR.

When set to 1, CPU1 element can cause a system Warm reset by setting AIRCR.SYSRESETREQ = 1.

The default value is 0, due to its interaction with the CryptoCell-312 core in the Subsystem.

TARGETIDSYS 0x07430477

Sets the Peripheral ID values for the CoreSight ROM table in the Debug element. A Debugger can read this value and discover the product that it connects to.

The system integrator must modify the value to use their JEP106 code and their part number for the product. See the Arm® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 for more information.

Two target system IDs must use different IDs unless the designs they identify are either:

  • Identical in all ways, including trigger network and the expansion part.
  • Some configurable pure subset, for example, configurable number of modules.
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