2.9.10 Wake From Hibernation using PD_SYS power control Q-Channel interface

Along with EWC, expansion blocks outside the subsystem can use the PD_SYS power control Q-Channel interface to wake the system from hibernation.

Waking the system using the interface does not, however, directly wake the cores or any other domains in this system unless accesses to the system result in a wake interrupt on an EWC, or an SRAM wake request, while accessing SRAM.


  • The system SYSCLK, and therefore also the MAINCLK, coming into the system might not be running during hibernation. A wake request on SYSPWRQACTIVE input automatically results in a request for MAINCLK to be active so that the Q-Channel handshake can be performed.
  • When the base system in the PD_SYS power domain wakes from hibernation, all registers in the domain are in reset state and all peripherals that reside behind the PPC and MPC default to Secure access only. There is typically a requirement to also wake and boot a processor to configure the system before allowing access for other masters to the system.

    Arm recommends that you do not depend on the PD_SYS power control Q-Channel interface to wake the system from hibernation and instead use interrupt signals on the EWC. This allows a request to wake a core which then in turn wakes the system and configures it before allowing other masters to access it.

    To delay access from other masters in the system, you must also deploy access control gates at slave expansion interfaces of the base system. The subsystem provides the ACC_WAITN register and the ACCWAITN signal to control access.

  • If you require the ability to wake and access the base system from the expansion interfaces without also waking a core, you must ensure the master accessing the system is a Secure master.

    When the system wakes without a processor restoring the configuration of all MPCs and PPCs in the system, your Secure master sees all Non-secure memory space as Secure memory space.

    You must ensure that if any of these Non-secure memories support retention, these memory locations are not used for code execution by Secure masters.

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