The nWARMRESETAON signal performs a System Warm reset. nWARMRESETAON is generated by merging reset requests from the following sources, possibly after masking with the value in the RESET_MASK register:

  • The system reset request from the Cortex®-M33 core.

nWARMRESETAON is provided to system designers for external components.


nWARMRESETAON resets PD_SRAM0, PD_SRAM3, PD_SYS, and PD_CRYPTO. The PPU generates the reset in each power domain including the nWARMRESETAON reset and the local power management reset. The PPU reset pin is either:

  • DEVWARMRESETn if the element does not support retention.
  • DEVRETRESETn if the element supports logic or full retention.
Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.