2.2.4 Power control expansion

Two clocks allow the system designer to add extra power control logic in the Always-On power domain:

  • CPUDEBUGPIKCLK is a hierarchically gated version of SYSCLK clock that is related to the nPORESETAON reset domain.

    The resynchronized reset signal for this clock is nCPUDEBUGPIKRESET.

    A Q-Channel interface is also provided to allow expansion logic on this clock domain to influence the hierarchical gating of the clock.

    This clock is typically used for power control logic that supports expansion of the CPU and Debug elements.

  • BCRYPTOSPIKCLK is a hierarchically gated version of SYSCLK that is related to the nWARMRESETAON reset domain.

    The resynchronized reset signal for this clock is nBCRYPTOSPIKRESET.

    A Q-Channel interface is provided to allow expansion logic on this clock domain to influence the hierarchical gating of the clock.

    This clock is typically used for power control logic that supports expansion of the main system that is reset directly or indirectly by nWARMRESETAON.

Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.