2.2.2 Clock generation and control

This section describes clock generation and control for MAINCLK, FCLK, SYSCLK, and clocks derived from them.


Most clocks within the subsystem are derived from MAINCLK, the subsystem main input clock. The following handshake signals control the clock state:

  • MAINCLKREQ is the system request for MAINCLK to become active.
  • MAINCLKRDY is the notification that MAINCLK is ready to be used.

MAINCLK is required in the following conditions:

  • Any PPU in the system is in the ON state.
  • Any External Wakeup Controller (EWC) is requesting that a core wakes up.
  • Expansion logic uses the EXPCLKREQ and EXPCLKRDY handshake logic to request that ungated clocks are available.

Therefore, MAINCLK can be turned off only when the system goes into the Hibernate state and no other parts of the system, including from external expansion logic, requests the clocks to be available.


FCLK and SYSCLK are generated from MAINCLK:

  • FCLK is generated by dividing MAINCLK.
  • SYSCLK is then generated by dividing FCLK.
  • The divider ratio can be set from configuration parameters and also by software.


When generating SYSCLK, ensure that the MAINCLK frequency, and the selected clock divider ratios for FCLK and SYSCLK, result in a SYSCLK frequency of more than double the S32KCLK frequency.

The subsystem uses the EXPCLKREQ and EXPCLKRDY handshake signals to provide SYSCLK and FCLK on request from external hardware. The handshake follows the same protocol as the MAINCLKREQ and MAINCLKRDY handshake signals. When using the EXPCLKREQ and EXPCLKRDY handshake signals to request active clocks, the SSE-200 also requests that the MAINCLK clock is active.


All signals described previously connect to and from the Always ON (AON) part of the system.

Clock and reset outputs are provided for expansion of other power domains within the subsystem as follows:

  • For the PD_SYS power domain, SYSFCLK and SYSSYSCLK are power-gated and hierarchical clock-gated versions of FCLK and SYSCLK. These are used for expansion logic that resides in the PD_SYS power domain. In additional SYSSYSUGCLK and SYSFUGCLK are the equivalent power-gated but not hierarchical clock-gated versions of SYSCLK and FCLK.
  • For the PD_DEBUG power domain, DEBUGFCLK and DEBUGSYSCLK are the PD_DEBUG power gated versions of FCLK and SYSCLK. These are used for debug expansion logic that resides in the PD_DEBUG power domain.
  • The HINTSYSCLKENCLK and DEBUGHINTSYSCLKENCLK signals are clock pulses that are generated by the divider to indicate when, relative to the divided clock FCLK or DEBUGFCLK, an enable must be generated. These are used by expansion logic external to the subsystem to generate the enables locally so that they can be used with bridges or other equivalent logic for crossing between FCLK and SYSCLK clock domains. The enables would normally occur at the last FCLK cycle prior to, and up to, the rising edge of SYSCLK. HINTSYSCLKENCLK is used to generate the enable in the AON domain while DEBUGHINTSYSCLKENCLK is used in the PD_DEBUG power domain to do the same.


All fast clock outputs, FCLK, SYSFCLK and DEBUGFCLK can be gated by HINTSYSCLKENCLK when CPU 1 in the system is turned off. To enable gating, set the FCLKHINTGATE_ENABLE bit in the CLOCK_FORCE register to 1.

This allows all logic that runs on the faster clock to run at the same clock speed as the rest of the system and reduces power consumption, but at the cost of slightly higher latency when accessing SRAM3.

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