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This section describes clock generation and control for MAINCLK, FCLK, SYSCLK, and clocks derived from them.
Most clocks within the subsystem are derived from MAINCLK, the subsystem main input clock. The following handshake signals control the clock state:
MAINCLKRDY is the notification that MAINCLK is ready to be used.
MAINCLK is required in the following conditions:
Therefore, MAINCLK can be turned off only when the system goes into the Hibernate state and no other parts of the system, including from external expansion logic, requests the clocks to be available.
FCLK and SYSCLK are generated from MAINCLK:
When generating SYSCLK, ensure that the MAINCLK frequency, and the selected clock divider ratios for FCLK and SYSCLK, result in a SYSCLK frequency of more than double the S32KCLK frequency.
The subsystem uses the EXPCLKREQ and EXPCLKRDY handshake signals to provide SYSCLK and FCLK on request from external hardware. The handshake follows the same protocol as the MAINCLKREQ and MAINCLKRDY handshake signals. When using the EXPCLKREQ and EXPCLKRDY handshake signals to request active clocks, the SSE-200 also requests that the MAINCLK clock is active.
Clock and reset outputs are provided for expansion of other power domains within the subsystem as follows:
All fast clock outputs, FCLK, SYSFCLK and DEBUGFCLK can be gated by HINTSYSCLKENCLK when CPU 1 in the system is turned off. To enable gating, set the FCLKHINTGATE_ENABLE bit in the CLOCK_FORCE register to 1.
This allows all logic that runs on the faster clock to run at the same clock speed as the rest of the system and reduces power consumption, but at the cost of slightly higher latency when accessing SRAM3.