A.3 AHB expansion bus signals

The following table lists the signals for the two system expansion AHB master interfaces.

Table A-3 External AHB target port signals

Signal name Width Direction Description
HSEL 1 Output Slave Select.
HADDR 32 Output Address bus.
HBURST 3 Output Burst type.
HMASTLOCK 1 Output Locked Sequence.
HPROT 7 Output Protection Control.
HSIZE 3 Output Transfer Size.
HNONSEC 1 Output Indicates that the current transfer is either a Non-secure transfer or a Secure transfer.
HEXCL 1 Output Exclusive Transfer. Indicates that the transfer is part of an Exclusive access sequence.
HMASTER 5 Output Master Select.
HTRANS 2 Output Transfer Type.
HWDATA 32 Output Write Data.
HWRITE 1 Output Transfer Direction.
HAUSER 2 Output Address USER signals (Not used by the SSE-200 processors).
HWUSER 2 Output Write-data USER signals (Not used by the SSE-200 processors).
HREADYMUX 1 Output HREADY feedback to all slaves.
HRUSER 2 Input Read-data USER signals (Not used by the SSE-200 processors).
HRDATA 32 Input Read data bus.
HREADYOUT 1 Input When HIGH, the HREADY signal indicates to the master and all slaves, that the previous transfer is complete.
HRESP 1 Input Transfer response.
HEXOKAY 1 Input Exclusive OK.

The following table lists the signals for the two AHB slave interfaces.

Table A-4 External AHB initiator port signals

Signal name Width Direction Description
HSEL 1 Input Slave Select.
HADDR 32 Input Address bus.
HBURST 3 Input Burst type.
HMASTLOCK 1 Input Locked Sequence.
HPROT 7 Input Protection Control.
HSIZE 3 Input Transfer Size.
HNONSEC 1 Input Indicates that the current transfer is either a Non-secure transfer or a Secure transfer.
HEXCL 1 Input Exclusive Transfer. Indicates that the transfer is part of an Exclusive access sequence.
HMASTER 4 Input Master Select.
HTRANS 2 Input Transfer Type.
HWDATA 32 Input Write Data.
HWRITE 1 Input Transfer Direction.
HAUSER 2 Input Address USER signals (Not used by the SSE-200 processors).
EXREQ 1 Input Exclusive Request signal.
HWUSER 2 Input Write-data USER signals (Not used by the SSE-200 processors).
HRUSER 2 Output Read-data USER signals (Not used by the SSE-200 processors).
HRDATA 32 Output Read data bus.
HREADY 1 Input HREADY feedback from interconnect.
HRESP 1 Output Transfer response.
HREADYOUT 1 Output When HIGH, the HREADY signal indicates to the master and all slaves, that the previous transfer is complete.
HEXOKAY 1 Output Exclusive OK.

The following table lists the signals on the code expansion bus:

Table A-5 External code bus signals

Signal name Width Direction Description
CODEEXPHSEL 1 Output Slave select.
CODEEXPHADDR 29 Output Address bus.
CODEEXPHBURST 3 Output Burst type.
CODEEXPHMASTLOCK 1 Output Locked sequence.
CODEEXPHPROT 7 Output Protection control.
CODEEXPHSIZE 3 Output Transfer size.
CODEEXPHNONSEC 1 Output Indicates that the current transfer is either a Non-secure transfer or a Secure transfer.
CODEEXPHEXCL 1 Output Exclusive transfer. Indicates that the transfer is part of an Exclusive access sequence.
CODEEXPHMASTER 5 Output Master select.
CODEEXPHTRANS 2 Output Transfer type.
CODEEXPHWDATA 32 Output Write data.
CODEEXPHWRITE 1 Output Transfer direction.
CODEEXPHAUSER 2 Output Address USER signals.
CODEEXPHWUSER 2 Output Write channel USER signals.
CODEEXPHREADYMUX 1 Output HREADY feedback to all slaves.
CODEEXPHRUSER 2 Input Read channel USER signals.
CODEEXPHRDATA 32 Input Read data bus.
CODEEXPHREADYOUT 1 Input When HIGH, the HREADY signal indicates to the master and all slaves, that the previous transfer is complete.
CODEEXPHRESP 1 Input Transfer response.
CODEEXPHEXOKAY 1 Input Exclusive OK.
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