About this book

This book is for the Arm® CoreLink™ SSE-200 Subsystem for Embedded (SSE-200). It provides a high-level overview of the SSE-200. It describes architectural information and, as such, facilitates the creation of software or a SoC targeted at an Internet of Things (IoT) application.

Product revision status

The rmpn identifier indicates the revision status of the product described in this book, for example, r1p2, where:

rmIdentifies the major revision of the product, for example, r1.
pnIdentifies the minor revision or modification status of the product, for example, p2.

Intended audience

This book is written for system designers, system integrators, and programmers who are designing or programming a System-on-Chip (SoC) that uses the SSE-200.

Using this book

This book is organized into the following chapters:

Chapter 1 Introduction

This chapter introduces the SSE-200.

Chapter 2 Functional description

This chapter describes the functionality of the SSE-200.

Chapter 3 Programmers Model

This chapter describes the SSE-200 memory regions and registers, and provides information on how to program a SoC that contains an implementation of the SSE-200.

Appendix A Signal Descriptions

This appendix summarizes the interface signals present in the SSE-200 elements.

Appendix B Revisions

This appendix describes the technical changes between released issues of this book.


The Arm® Glossary is a list of terms used in Arm documentation, together with definitions for those terms. The Arm Glossary does not contain terms that are industry standard unless the Arm meaning differs from the generally accepted meaning.

See the Arm® Glossary for more information.

Typographic conventions
Introduces special terminology, denotes cross-references, and citations.
Highlights interface elements, such as menu names. Denotes signal names. Also used for terms in descriptive lists, where appropriate.
Denotes text that you can enter at the keyboard, such as commands, file and program names, and source code.
Denotes a permitted abbreviation for a command or option. You can enter the underlined text instead of the full command or option name.
monospace italic
Denotes arguments to monospace text where the argument is to be replaced by a specific value.
monospace bold
Denotes language keywords when used outside example code.
Encloses replaceable terms for assembler syntax where they appear in code or code fragments. For example:
MRC p15, 0, <Rd>, <CRn>, <CRm>, <Opcode_2>
Used in body text for a few terms that have specific technical meanings, that are defined in the Arm® Glossary. For example, IMPLEMENTATION DEFINED, IMPLEMENTATION SPECIFIC, UNKNOWN, and UNPREDICTABLE.
Timing diagrams

The following figure explains the components used in timing diagrams. Variations, when they occur, have clear labels. You must not assume any timing information that is not explicit in the diagrams.

Shaded bus and signal areas are undefined, so the bus or signal can assume any value within the shaded area at that time. The actual level is unimportant and does not affect normal operation.

Figure 1 Key to timing diagram conventions
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The signal conventions are:

Signal level

The level of an asserted signal depends on whether the signal is active-HIGH or active-LOW. Asserted means:

  • HIGH for active-HIGH signals.

  • LOW for active-LOW signals.

Lowercase n

At the start or end of a signal name denotes an active-LOW signal.

Additional reading

This book contains information that is specific to this product. See the following documents for other relevant information.

Arm publications
  • Arm® CoreLink™ SSE-200 Subsystem for Embedded Technical Reference Manual (Arm 101104)
  • Arm® CoreLink™ SIE-200 System IP for Embedded Technical Reference Manual (Arm DDI 0571).
  • Arm® Cortex®-M System Design Kit Technical Reference Manual (Arm DDI 0479).
  • Arm® Cortex®-M33 Processor Technical Reference Manual (Arm 100230).
  • Arm® Power Policy Unit Architecture Specification, version 1.1 (Arm DEN 0051).
  • Arm® CoreSight™ Architecture Specification, v2.0 (Arm IHI 0029).
  • Arm® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 (Arm IHI 0031).
  • Arm® CoreSight™ Components Technical Reference Manual (Arm DDI 0314).
  • Arm® Embedded Trace Macrocell (ETMv4) Architecture Specification (Arm IHI 0064).
  • Arm® AMBA® 5 AHB Protocol Specification (Arm IHI 0033).
  • Arm® AMBA® APB Protocol Specification Version 2.0 (Arm IHI 0024).
  • Arm® CoreSight™ DAP-Lite Technical Reference Manual (Arm DDI 0316D).

The following confidential books are only available to licensees or require registration with Arm:

  • Arm® CoreLink™ SSE-200 Subsystem for Embedded Configuration and Integration Manual (Arm 100224).
  • Arm® CoreLink™ SSE-200 Subsystem for Embedded Release Note (CG062‑DC‑06003).
  • Arm® Cortex®-M33 Processor User Guide Reference Material (Arm 100234).
  • Arm®v7-M Architecture Reference Manual (Arm DDI 0403).
  • Arm®v8-M Architecture Reference Manual (Arm DDI 0553).
  • Arm® Cortex®-M33 Processor Integration and Implementation Manual (Arm 100323).
  • AMBA® Low Power Interface Specification, Arm® Q-Channel and P-Channel Interfaces (Arm IHI 0068).
  • Arm® Debug Interface Architecture Specification ADIv5.0 to ADIv5.2 (Arm IHI 0031).
  • Arm® TrustZone® CryptoCell-312 Technical Reference Manual (Arm 100774).
  • Arm® CoreSight™ SoC-400 Technical Reference Manual (Arm 100536).
  • Arm® CoreSight™ SoC-400 System Design Guide (Arm 100495).
  • Arm® CoreSight™ SoC-400 User Guide (Arm DUI 0563).
  • Arm® CoreLink™ SSE-200 Subsystem for Embedded Analysis Report (PJDOC‑1779577084‑8399).
Other publications
Non-ConfidentialPDF file icon PDF version101104_0200_00_en
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