3.3.1 Processor L1 cache registers

The following table lists the cache registers. All registers are Secure privileged access only.

Table 3-6 Summary of processor L1 cache registers

Offset Register name Access Reset value Full name
0x000 ICHWPARAMS RO Depends on configuration. Hardware Parameter register, ICHWPARAMS
0x004 ICCTRL RW 0x04 Instruction Cache Control Register, ICCTRL
0x008-0x0FC - - - Reserved.
0x100 ICIRQSTAT RO 0x0 Interrupt Request Status register, see Instruction Cache Interrupt Registers, ICIRQSTAT, ICIRQSCLR, and ICIRQEN.
0x104 ICIRQSCLR WO 0x0 Interrupt Status Clear register
0x108 ICIRQEN RW 0x0 Interrupt Enable register
0x10C ICDBGFILLERR RO 0x0 Debug Fill Error Register, ICDBGFILLERR.
0x200-0x2FC - - - Reserved.
0x300 ICSH RO 0x0 Instruction Cache Statistic Hit register, ICSH.
0x304 ICSM RO 0x0 Instruction Cache Statistic Miss Count register, ICSM.
0x308 ICSUC RO 0x0 Instruction Cache Statistic Uncached Count register, ICSUC.
0x30C-0xFCC - - - Reserved.
0xFD0 PIDR4 RO 0x04 Product ID Register 4.
0xFD4 PIDR5 RO 0x0 Product ID Register 5.
0xFD8 PIDR6 RO 0x0 Product ID Register 6.
0xFDC PIDR7 RO 0x0 Product ID Register 7.
0xFE0 PIDR0 RO 0x57 Product ID Register 0.
0xFE4 PIDR1 RO 0xB8 Product ID Register 1.
0xFE8 PIDR2 RO 0x01B Product ID Register 2.
0xFEC PIDR3 RO 0x00 Product ID Register 3.
0xFF0 CIDR0 RO 0x0D Component ID Register 0.
0xFF4 CIDR1 RO 0xF0 Component ID Register 1.
0xFF8 CIDR2 RO 0x05 Component ID Register 2.
0xFFC CIDR3 RO 0xB1 Component ID Register 3.

Hardware Parameter register, ICHWPARAMS

The ICHWPARAMS is a read-only register that describes the instruction cache configuration.

Table 3-7 ICHWPARAMS register

Bits Name Access Reset value Description
[31:16] COFFSET RO 0x0 Cacheable Offset Address. Set the top address bits[31:16] of the cacheable address region.
[15:12] COFFSIZE RO 0x3

Cacheable Block Size. Sets the block size of the cacheable region and also indicates the number of top address bits on an access that is not used in cache lookup but is compared against the top bits of COFFSET, for example:

0x0: 4GB

0x1: 2GB

0x2: 1GB

0x3: 512MB

[11:7] Reserved RO - Reserved.
[6] INVMAT RO Parameterized Indicates invalidate cache line on write match is enabled. This bit depends on CPU0_ICACHEINVMAT for CPU0, or CPU1_ICACHEINVMAT for CPU1.
[5] DMA RO 0x0

Presence of DMA Engine:

0 = Instruction cache does not support prefetch and locking.

[4] STATS RO 0xParameterized Presence of Statistic Functionality.
[3:0] CSIZE RO Parameterized

Cache size. Defines the size of the instruction cache:

9: 512 byte

10: 1 KB

11: 2 KB

12: 4 KB

13: 8 KB

14: 16 KB

Other values are reserved.

Instruction Cache Control Register, ICCTRL

The ICCTRL register allows software to control the cache. This includes enabling or disabling the cache, starting invalidations and configuring what must be cached or uncached based on the HHINT[2] signal from the processor.

For write accesses, this register only supports 32-bit writes. Any write that is not 32 bits is ignored.

Table 3-8 ICCTRL register

Bits Name Access Reset value Description
[31:7] Reserved RO 0x0 -
6 POINV_SMP RO 0x1 Power On Invalidate (POINV) port sampled value, for determining Power-on-invalidate functionality.
5 HALLOC RW 0x0 Enable Handler Allocation:
  • When set to LOW, all incoming handler code fetches are not allocated a cache line if a miss occurs. If the fetch results in a hit in the cache, the access is treated as if it is cached.

    HALLOC LOW allows handler code accesses to be more deterministic. It also avoids cache trashing if there are many interrupt service routines.

    HALLOC has no effect on DMA fetches and line locking.

  • When HALLOC is set to HIGH, then handler code access is treated like any other code access arriving at its interface.
4 STATC WO 0x0 Clear Statistic values. Writing a 1 to this register triggers the instruction cache to start clear all cache statistic counters.
3 STATEN RW 0x0 Enable Statistic function. When set to 1, cache statistic counters are enabled. When set to 0, cache statistic counters are disabled.
2 FINV WO 0x0 Full Cache Invalidate. Writing a 1 to this register triggers the instruction cache to start invalidating all cache lines.
1 Reserved RO 0x0 Reserved.
0 CACHEEN RW 0x0 Enable Cache. When set to 1, caching is enabled. When set to 0, all accesses bypass the cache.

Instruction Cache Interrupt Registers, ICIRQSTAT, ICIRQSCLR, and ICIRQEN

The instruction cache interrupt registers allow software to determine the source of an interrupt coming from the instruction cache. They also allow software to clear, disable, or enable the interrupts:

  • ICIRQSTAT is read-only (RO). The Instruction Cache Interrupt Status register holds the status of all interrupts before being masked.
  • ICIRQSCLR is write-only (WO). The Instruction Cache Interrupt Clear register allows the status of active interrupts to be cleared by writing a 1 to is associated field.
  • ICIRQEN is read/write (RW). The Instruction Cache Interrupt Masks register allows each interrupt status to be enabled or disabled from driving the instruction cache interrupt signal.

All interrupt registers share fields, as the following table shows.

Note:

When enabling an interrupt, it is possible to receive an interrupt immediately on the disable event if that interrupt event occurred before the programming event.

Table 3-9 Instruction cache interrupt registers

Bits Name Reset value Description
[31:6] - 0x0 Reserved.
[5] SS 0 Statistics Saturated IRQ. Indicates that the internal statistic counters have saturated.
[4] SV 0 Security violation IRQ status.
[3] CFE 0 Cache Fill Error IRQ. Indicates that a bus error occurred while filling a cache line.
[2] CEC 0 Cache Enable Complete IRQ. Indicates that a request to enable the cache has been completed.
[1] CDC 0 Cache Disable Complete IRQ. Indicates that a request to disable the cache has been completed.
[0] IC 0 Invalidate Complete IRQ. Indicates that a cache invalidation process has been completed.

Debug Fill Error Register, ICDBGFILLERR

The ICDBGFILLERR register allows software to discover the address that is involved in a recent fill error.

Table 3-10 ICDBGFILLERR register

Bits Name Access Reset value Description
[31:0] ERRADDR RO 0x0 Address where the latest fill error was seen.

Note:

The address might change between the associated interrupt and the read by the processor, and is therefore intended only as a crude debug assist.

The two least significant bits of this register always return zeros.

Instruction Cache Statistic Hit register, ICSH

The ICSH allows software to read the instruction cache hit counter value.

This register counts the number of read accesses that results in cache hits since the last counter clear operation. This register ignores write accesses.

Table 3-11 ICSHR register

Bits Name Access Reset value Description
[31:0] CSHR RO 0x0 Cache Hit Counter.

Instruction Cache Statistic Miss Count register, ICSM

The ICSM register allows software to read the instruction cache miss counter value. This register counts the number of read accesses that results in cache misses since the last counter clear operation. This register ignores write accesses.

Table 3-12 ICSM register

Bits Name Access Reset value Description
[31:0] CSM RO 0x0 Cache miss counter.

Instruction Cache Statistic Uncached Count register, ICSUC

The ICSUC register allows software to read the instruction cache uncached access counter value. This register counts the number of uncached read accesses seen by the instruction cache since the last counter clear operation. This register ignores write accesses.

Table 3-13 ICSUC register

Bits Name Access Reset value Description
[31:0] CSUC RO 0x0 Uncached access counter.

CIDRx, PIDRx

The CIDR and PIDR registers are statically configured at compile time. PIDR3 is specified from a static register to allow ECO modifications to the identity.

The default values are listed in the following tables.

Table 3-14 Product and component ID registers

Name Function Access Reset value Description
PIDR0 Part number RO 0x57 Product ID Register 0.
PIDR1 Part number RO 0xB8 Product ID Register 1.
PIDR2 Part revision RO 0x01B Product ID Register 2.
PIDR3 Revision number RO 0x00 Product ID Register 3.
PIDR4 Reserved RO 0x04 Product ID Register 4.
PIDR5 Reserved RO 0x00 Product ID Register 5.
PIDR6 Reserved RO 0x00 Product ID Register 6.
PIDR7 Reserved RO 0x00 Product ID Register 7.
CIDR0 Preamble RO 0x0D Component ID Register 0.
CIDR1 Preamble RO 0xF0 Component ID Register 1.
CIDR2 Preamble RO 0x05 Component ID Register 2.
CIDR3 Preamble RO 0xB1 Component ID Register 3.
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