A.6.2 Top-level static configuration signals

The following table lists the static configuration signals that are at the top level of the SSE-200. These static signals are asynchronous and are expected to be unchanged after de-assertion of Power-on reset.

Table A-20 Top-level static configuration signals

Signal name Width Direction Description
SYSCLKENTRYDELAY 8 Input The SYSCLKENTRYDELAY defines the number of delay cycles that a SYSCLK-related hierarchical clock gated domain is idle before clocks are sequenced to turn off.
FCLKENTRYDELAY 8 Input The FCLKENTRYDELAY defines the number of delay cycles that an FCLK-related hierarchical clock gated domain is idle before clocks are sequenced to turn off.
INITSVTOR0_RST 25 Input Reset Value of the CPU 0 (Primary) Secure Vector table offset present in the address register in the System Control Register
INITSVTOR1_RST 25 Input Reset Value of the CPU 1 (Secondary) Secure Vector table offset present in the address register in the System Control Register.
CTMCHCISBYPASS 1 Input

Defines if the CTMCHIN and CTMCHOUTACK[3:0] of the Cross Trigger Channel Interface is synchronous or asynchronous to the DEBUGSYSCLK:

0: Asynchronous. Signals are resynchronized internally.

1: Synchronous. Signals are not resynchronized internally.

CTMCHCIHSBYPASS 4 Input

Defines whether the handshake logic that is associated to each CTMCHOUT pin is used.

Tie HIGH to disable the handshake logic.

Handshake logic is not required if CTMCHOUT drives synchronous logic.

TINIDENSEL 8 Input NIDEN mask on CTITRIGIN. When each bit is set to LOW, it masks the associated Cross Trigger Interface’s trigger input when NIDEN is LOW.
TIHSBYPASS 4 Input Cross Trigger interface handshake bypass on CTITRIGOUT. Tie each bit to HIGH to disable the associated handshake logic on the respective CTITRIGOUT bit.
TISBYPASSACK 4 Input Cross Trigger Interface synchronous bypass on CTITRIGOUTACK. If a CTITRIGOUTACK input is synchronous to DEBUGSYSCLK, and is driven from the same clock domain, tie its associated TISBYPASSACK pin HIGH to bypass the synchronization logic.
TISBYPASSIN 8 Input Cross Trigger Interface synchronous bypass on CTITRIGIN. If a CTITRIGIN input is synchronous to DEBUGSYSCLK, and is driven from the same clock domain, tie its associated TISBYPASSIN pin HIGH to bypass the synchronization logic.
TODBGENSEL 4 Input DBGEN mask on CTITRIGOUT. When each bit is set to LOW, it masks the associated Cross Trigger Interface’s trigger output when DBGEN is LOW.
DBGENSELDIS 1 Input DBGEN Selector Disable. When set HIGH, disables the DBGEN Selector Logic and forces DBGEN to use DBGENIN. If the Crypto element exists, this must be tied to HIGH.
NIDENSELDIS 1 Input NIDEN Selector Disable. When set HIGH, disables the NIDEN Selector Logic and forces NIDEN to use NIDENIN. If the Crypto element exists, this must be tied to HIGH.
SPIDENSELDIS 1 Input SPIDEN Selector Disable. When set to HIGH disables the SPIDEN Selector Logic and forces SPIDEN to use SPIDENIN. If the Crypto element exists, this must be tied to HIGH.
SPNIDENSELDIS 1 Input SPNIDEN Selector Disable. When set to HIGH disables the SPNIDEN Selector Logic and forces SPNIDEN to use SPNIDENIN. If the Crypto element exists, this must be tied to HIGH.

Note:

For a top-level definition of the configuration points that are used to render the design to the build system, see Arm® CoreLink™ SSE-200 Subsystem for Embedded Configuration and Integration Manual.
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