2.8.5 CoreSight debug ROM tables

There are three CoreSight™ ROM tables that are implemented within the SSE-200 subsystem in addition to the processor core.

Debug system CoreSight ROM table

The debug system CoreSight ROM is only accessible from the debug system Access APB-AP. It is at address 0xF000_0000.

The following table shows the contents of the ROM table. The PID values depend on the value of the TARGETIDSYS[31:0] static configuration signal, which by default is set to 0x0743_0477.

Table 2-10 Debug system ROM table

Address offset Value Description
0x000 0x0000_1003 Entry points to the debug element trace funnel.
0x004 0xF00F_7007 Entry points to the debug element CTI.
0x008 0x0008_0003 Entry points to an external ROM on the APB expansion region.
0x00C-0xEFC 0x0000_0000 Unused ROM entries.
0xF00-0xFC8 0x0000_0000 Reserved.
0xFCC 0x0000_0000 MEMTYPE register.
0xFD0 0x0000_0004 Peripheral ID, PIDR4. PIDR4[3:0] is the JEP106 continuation code, which is set by TARGETIDSYS[11:8].
0xFD4 0x0000_0000 Peripheral ID, PIDR5
0xFD8 0x0000_0000 Peripheral ID, PIDR6
0xFDC 0x0000_0000 Peripheral ID, PIDR7
0xFE0 0x0000_0043 Peripheral ID, PIDR0. PIDR0[7:0] is the Part Number bits [7:0], which is set by TARGETIDSYS[23:16].
0xFE4 0x0000_00B7

Peripheral ID, PIDR1. PIDR1[3:0] is the Part Number [11:8], which is set by TARGETIDSYS[27:24].

PIDR1[7:4] is the JEP106 Identity Code [3:0], which is set by TARGETIDSYS[4:1].

0xFE8 0x0000_000B

Peripheral ID, PIDR2. PIDR2[2:0], is the JEP106 Identity Code [6:4], which is set by TARGETIDSYS[7:5].

PIDR2[3] is the JEDEC identifier.

PIDR2[7:4] is the Revision Code, which is set by TARGETIDSYS[31:28].

0xFEC 0x0000_0000 Peripheral ID, PIDR3
0xFF0 0x0000_000D Component ID, CID0
0xFF4 0x0000_0010 Component ID
0xFF8 0x0000_0005 Component ID, CID2
0xFFC 0x0000_00B1 Component ID, CID3

CPU access CoreSight ROM table

There up to two CPU System CoreSight ROMs, one for each processor. Each ROM is accessible through its associated CPU Access AHB-AP. It is at address 0xF000_8000.

The following table lists the contents of the ROM table.

Table 2-11 CPU access ROM table

Address offset Value Description
0x000 0x0000_1003 Entry points to the Granular Power Requester.
0x004 0x0000_2003 Entry points to the internal ROM table for the processor.
0x008-0xEFC 0x0000_0000 Unused ROM entries.
0xF00-0xFC8 0x0000_0000 Reserved.
0xFCC 0x0000_0000 MEMTYPE register.
0xFD0 0x0000_0004 Peripheral ID, PIDR4.
0xFD4 0x0000_0000 Peripheral ID, PIDR5.
0xFD8 0x0000_0000 Peripheral ID, PIDR6.
0xFDC 0x0000_0000 Peripheral ID, PIDR7.
0xFE0 0x0000_0043 Peripheral ID, PIDR0.
0xFE4 0x0000_00B7 Peripheral ID, PIDR1.
0xFE8 0x0000_000B Peripheral ID, PIDR2.
0xFEC 0x0000_0000 Peripheral ID, PIDR3.
0xFF0 0x0000_000D Component ID, CID0.
0xFF4 0x0000_0010 Component ID, CID1.
0xFF8 0x0000_0005 Component ID, CID2.
0xFFC 0x0000_00B1 Component ID, CID3.
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