A.2 Interrupt signals

The following table lists interrupt signals in the SSE-200 interface. These connect to the interrupt controller of each processor within the SSE-200 through an External Wakeup Controller (EWC) associated with the processor, and the Wakeup Interrupt Controller (WIC) of the Cortex®-M33.

Table A-2 Interrupt signals

Signal name Width Direction Description
CPU0EXPIRQ[CPU0_EXP_NUMIRQ-1:0] CPU0_EXP_NUMIRQa Input

These are interrupt inputs from the expansion subsystem to the CPU 0 interrupt controller within the SSE-200. The processor in the SSE-200 implements a configurable number of external interrupt lines and 32 of these are reserved for internal use, and the remaining are made available here.

Note:

Each bit CPU0EXPIRQ[n] is ultimately connected to IRQ[32+n] of the NVIC for CPU 0.
CPU1EXPIRQ[CPU1_EXP_NUMIRQ-1:0] CPU1_EXP_NUMIRQb Input

These are interrupt inputs from the expansion subsystem to the CPU 1 interrupt controller within the SSE-200. The processor in the SSE-200 implements a configurable number of external interrupt lines and 32 of these are reserved for internal use, and the remaining are made available here.

Note:

Each bit CPU1EXPIRQ[n] is ultimately connected to IRQ[32+n] of the NVIC for CPU 1. If the system is configured to not include CPU 1, then this interface does not exist.

.

CPU0EXPNMI 1 Input This provides a non-maskable interrupt input from the expansion subsystem to the interrupt controller of CPU 0 within the SSE-200. This input is merged with other non-maskable interrupt sources within the SSE-200 before it is seen by the NVIC of the core.
CPU1EXPNMI 1 Input This provides a non-maskable interrupt input from the expansion subsystem to the interrupt controller of CPU 1 within the SSE-200. This input is merged with other non-maskable interrupt sources within the SSE-200 before it is seen by the NVIC of the core. If the system is configured to not include CPU 1, then this interface does not exist.
a CPU0_EXP_NUMIRQ defines the number of interrupts made available as expansion interrupts for CPU 0.
b CPU1_EXP_NUMIRQ defines the number of interrupts made available as expansion interrupts for CPU 1.
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