3.3.6 PPB regions

The Private Peripheral Bus (PPB) includes the following regions that provide access to the processor core internal processor resources:

  • The Instrumentation Trace Macrocell (ITM) if included.
  • The Data Watchpoint and Trace (DWT) if included.
  • The Flash Patch and Breakpoint (FPB) if included.
  • The System Control Space (SCS) which includes the Memory Protection Unit (MPU) and the Nested Vectored Interrupt Controller (NVIC).
  • The Embedded Trace Macrocell (ETM), if included.
  • The Cross Trigger Interface (CTI), if included.
  • The debug ROM table.

This memory region is as defined in the Arm®v8-M Architecture Reference Manual and the Arm® Cortex®-M33 Processor Integration and Implementation Manual.

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