2.4.2 Cortex-M33 configurations

Each processor supports the following configuration with the following features.

Table 2-1 Core configurations

Parameter CPU 0 option CPU 1 option CPU 0 default CPU 1 default Description
FPU CPU0_FPU CPU1_FPU 0 HAS_FPU

Define if Floating Point Unit (FPU) is present:

0: Not Present.

1: Present.

DSP CPU0_DSP CPU1_DSP 0 1

Digital Signal Processing (DSP) extension instructions are included.

0: Not included.

1: Included.

SECEXT 1 1 - - Arm®v8-M Security Extensions are always included.
CPIF CPU0_CPIF CPU1_CPIF 0 0

Coprocessor interface is included.

0: Not included. This is the only supported value.

1: Included.

These are driven by top-level parameters.

MPU_NS CPU0_MPU_NS CPU1_MPU_NS 8 8

Defines the number of Non-secure Memory Protection Unit (MPU) regions included.

Options are: 0, 4, 8, 12, and 16.

MPU_S CPU0_MPU_S CPU1_MPU_S 8 8

Defines the number of Secure MPU regions included.

Options are: 0, 4, 8, 12, and 16.

SAU CPU0_SAU CPU1_SAU 8 8

Defines the number of Security Attribution Unit (SAU) regions included.

Options are: 0, 4, and 8.

NUMIRQ CPU0_EXP_NUMIRQ + 32 CPU1_EXP_NUMIRQ + 32 64 + 32 = 96 64 + 32 = 96 Number of user interrupts implemented.
IRQLVL CPU0_IRQ_LVL CPU1_IRQ_LVL 4 4

Specifies the number of bits of interrupt priority that is implemented in the NVIC.

Supports a range of 3-8.

For example, a value of 3 results in eight levels of priority.

IRQLATENCY

IRQLATENCY[31:0] = CPU0_INT_IRQLATENCY[31:0] IRQLATENCY[CPU0_EXP_NUMIRQ+32:32] = CPU0_EXP_IRQLATENCY

IRQLATENCY[31:0] = CPU1_INT_IRQLATENCY[31:0] IRQLATENCY[CPU1_EXP_NUMIRQ+32:32] = CPU1_EXP_IRQLATENCY

- - Set interrupt latency.
IRQDIS

IRQDIS[7:0] = 8h00, IRQDIS[17:9] = 9h20, IRQDIS[31:21] = 11h641, If HAS_CRYPTO = 1: IRQDIS[8] == 0, IRQDIS[20] == 0, else: IRQDIS[8] == 1, IRQDIS[20] == 1. If SEPARATE_CPUDBG is True: IRQDIS[18] == 0, IRQDIS[19] == 0, else: IRQDIS[18] == 1, IRQDIS[19] == 1.

IRQDIS[7:0] = 8h00, IRQDIS[17:9] = 9h20, IRQDIS[31:21] = 11h641, If HAS_CRYPTO = 1: IRQDIS[8] == 0, IRQDIS[20] == 0, else: IRQDIS[8] == 1, IRQDIS[20] == 1. If SEPARATE_CPUDBG is True: IRQDIS[18] == 0, IRQDIS[19] == 0, else: IRQDIS[18] == 1, IRQDIS[19] == 1.

IRQDIS[479:32] = 448hAAAA,

For IRQDIS[31:0], see cells to the left.

IRQDIS[479:32] = 448hFF00,

For IRQDIS[31:0], see cells to the left.

Disable support for interrupt. Each bit in IRQDIS corresponds to an interrupt.

If the value of a bit in IRQDIS is 1, the corresponding IRQ is not present.

DBGLVL CPU0_DBGLVL CPU1_DBGLVL 2 2

Specifies the number of debug resources included. The options are:

0: minimal debug. Not supported.

1: reduced set. Two watchpoint and four breakpoint comparators.

2: full set. Four watchpoint and eight breakpoint comparators.

Debug monitor mode is always supported.

ITM 1 1 - -

Specifies the level of instrumentation trace supported. The options are:

0: No Instrumentation Trace Macrocell (ITM) trace included. DWT triggers and counters are not included.

1: Include DWT and ITM trace.

ETM 1 1 - -

Specifies support for ETM trace. The options are:

0: No ETM trace included.

1: ETM is included.

MTB 0 0 - -

Specifies support for MTB trace. The options are:

0: No MTB trace included.

1: MTB included.

MTBWIDTH 12 12 - - 12-bit MTB RAM interface address width. Not used.
WIC 1 1 - - WIC included.
WICLINES CPU0_EXP_NUMIRQ + 35 CPU1_EXP_NUMIRQ + 35 - - All interrupts are sensitive to WIC.
CTI 1 1 - - CTI included.
RAR 1 1 - - Only reset the architecturally required state.

Configuration signals from the SSE-200 determine some of the Cortex®-M33 processor options.These configuration signals are listed in the following table.

Table 2-2 Static configuration signals for the Cortex-M33 processor

Signal name Tie value Description
CFGBIGEND 0 Little-endian data endianness.
CFGSSTCALIB[25:0] 0x200_0000

Secure SysTick calibration configuration. No alternative reference clock is provided, and the frequency of the clock arriving at the processor is not computable in hardware.

CFGSSTCALIB[25]
NOREF = HIGH.
CFGSSTCALIB[24]
SKEW = LOW.
CFGSSTCALIB[23:0]
TENMS = 0x00_0000.
CFGNSSTCALIB[25:0] 0x200_0000

Non-secure SysTick calibration configuration indicating that no alternative reference clock is provided, and the frequency of clock arriving at the processor is not computable in hardware.

CFGNSSTCALIB[25]
NOREF = HIGH.
CFGNSSTCALIB[24]
SKEW = LOW.
CFGNSSTCALIB[23:0]
TENMS = 0x00_0000.
CFGFPU 1 FPU hardware support enabled.
CFGDSP 1 DSP hardware support enabled.
CFGSECEXT 1 Armv8-M security support enabled.
MPUNSDISABLE 0 Disables support for the Non-secure MPU. Set to LOW to not disable.
MPUSDISABLE 0 Disables support for the Secure MPU. Set to LOW to not disable.
SAUDISABLE 0 Disables support for the SAU. Set to LOW to not disable.

Both of the Cortex-M33 processors have a LOCKSMPU static configuration signal that has the following functions:

  • When HIGH, the signal disables writes to the MPU_CTRL, MPU_RNR, MPU_RBAR, MPU_RLAR, MPU_RBAR_An, and MPU_RLAR_An registers from software or from a debug agent connected to the processor.
  • When asserted, this signal prevents changes to programmed Secure MPU memory regions and all writes to the registers are ignored.
  • Locking of the Secure MPU is not supported.

When both CPU0 and CPU1 exist in the system, the event interfaces of both processors cross connect, so that one processor raises an event with the other. Events can be used with WFE instructions, which also allow the processor to be placed into a lower power state if necessary. If only one processor is configured, the event interface input is tied LOW and the output is not used.

Note:

Arm expects the event interfaces are used to communicate near term events between the cores. The architecture does not have the provision to be able to use events to wake a processor core that is in a powered off state. This architecture, however, does support waking the core from retention or clock-off lower power state. In addition, event interfaces on their own, like interrupts, cannot differentiate events that occur close together. It is difficult to count the high frequency events that occur close together. For example, when the difference in clock speed between both processors is large, or the software handler that is required to deal with events is slow.

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