3.4.7 Non-secure Privilege Control Block

The Non-secure Privilege Control Block implements program visible states that allow software to control various security gating units within the design.

This register is Non-secure privileged access only and supports 32-bit R/W access. Any byte and halfword writes are ignored.

This register block base address is 0x4008_0000. The following table shows the Non-secure privilege control registers.

Table 3-56 Summary of Non-secure Privilege Control registers

Offset Name Access Reset value Description
0c0000x06C Reserved - - Reserved.
0x090 AHBNSPPPC0 RW 0x0 Non-secure Unprivileged Access AHB slave Peripheral Protection Control #0. Each bit in this register defines the non-Secure unprivileged access settings for an associated AHB slave peripheral.
0x0940x09C Reserved RO 0x0 Reserved.
0x0A0 AHBNSPPPCEXP0 RW 0x0 Expansion 0 Non-secure Unprivileged Access AHB slave Peripheral Protection Control. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0A4 AHBNSPPPCEXP1 RW 0x0 Expansion 1 Non-secure Unprivileged Access AHB slave Peripheral Protection Control. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0A8 AHBNSPPPCEXP2 RW 0x0 Expansion 2 Non-secure Unprivileged Access AHB slave Peripheral Protection Control. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0AC AHBNSPPPCEXP3 RW 0x0 Expansion 3 Non-secure Unprivileged Access AHB slave Peripheral Protection Control. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0B0 APBNSPPPC0 RW 0x0 Non-secure Unprivileged Access APB slave Peripheral Protection Control 0. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0B4 APBNSPPPC1 RW 0x0 Non-secure Unprivileged Access APB slave Peripheral Protection Control 1. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0B80x0BC Reserved - 0x0 Reserved
0x0C0 APBNSPPPCEXP0 RW 0x0 Expansion 0 Non-secure Unprivileged Access APB slave Peripheral Protection Control. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0C4 APBNSPPPCEXP1 RW 0x0 Expansion 1 Non-secure Unprivileged Access APB slave Peripheral Protection Control. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0C8 APBNSPPPCEXP2 RW 0x0 Expansion 2 Non-secure Unprivileged Access APB slave Peripheral Protection Control. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0CC APBNSPPPCEXP3 RW 0x0 Expansion 3 Non-secure Unprivileged Access APB slave Peripheral Protection Control. Each bit in this register defines the Non-secure unprivileged access settings for an associated peripheral.
0x0D00xFCC Reserved - 0x0 Reserved
0xFD0 PIDR4 RO 0x0 Peripheral ID 4
0xFD4 Reserved RO 0x0 Reserved
0xFD8 Reserved RO 0x0 Reserved
0xFDC Reserved RO 0x0 Reserved
0xFE0 PIDR0 RO 0x0000_0053 Peripheral ID 0
0xFE4 PIDR1 RO 0x0000_00B8 Peripheral ID 1
0xFE8 PIDR2 RO 0x0000_000B Peripheral ID 2
0xFEC PIDR3 RO 0x0000_0000 Peripheral ID 3
0xFF0 CIDR0 RO 0x0000_000D Component ID 0
0xFF4 CIDR1 RO 0x0000_00F0 Component ID 1
0xFF8 CIDR2 RO 0x0000_0005 Component ID 2
0xFFC CIDR3 RO 0x0000_00B1 Component ID 3

AHBNSPPPC0

Non-secure Unprivileged Access AHB Slave Peripheral Protection Controller Register allows software to configure if each AHB peripheral that it controls from an AHB PPC is Non-secure privileged access only or is allowed Non-secure Unprivileged access. Each field defines this for an associated peripheral, by the following settings:

  • 1: Allow Non-secure unprivileged and privileged access.
  • 0: Allow Non-secure privileged access only.

SSE-200 does not have an AHB slave interface that needs Non-secure Unprivileged Access configuration support of the PPC. This register is reserved and RAZ/WI.

Table 3-57 AHBNSPPPC0 register

Bits Name Access Reset value Description
[31:0] Reserved RO 0x0 Reserved

AHBNSPPPCEXP0, AHBNSPPPCEXP1, AHBNSPPPCEXP2, and AHBNSPPPCEXP3

The Expansion Non-secure Privilege Access AHB Slave Peripheral Protection Controller Register 0, 1, 2 and 3 allow software to configure each AHB peripheral that it controls from each AHB PPC. These PPCs reside in the expansion subsystem outside of the SSE-200, and only Non-Secure privileged access only or both Non-Secure unprivileged and privileged access are allowed. Each field defines these conditions for an associated peripheral, by the following settings:

  • 1: Allow Non-secure unprivileged and privileged access.
  • 0: Allow Non-secure privileged access only.

These bits directly control the expansion signals on the Security Control Expansion interface.

All four registers are similar. The bits for register N, where N is from 0-3, are listed in the following table.

Table 3-58 AHBNSPPPCEXP<N> register

Bits Name Access Reset value Description
[31:16] Reserved RO 0x0 Reserved
[15:0] AHBNSPPPCEXP<N> RW 0x0

Expansion N Non-secure Privilege Access AHB slave Peripheral Protection Control. Each bit n drives the output signal AHBPPPCEXP<N>[n] HIGH if AHBNSPPCEXP<N>[n] signal is HIGH, where N is 0-3.

The parameter AHBPPCEXP_DIS<N> defines if each bit within this register is implemented so that if AHBPPCEXP_DIS<N>[i] = 1, AHBNSPPPCEXP<N>[i] is disabled, it reads as zeros, and any writes to it are ignored.

APBNSPPPC0 and APBNSPPPC1

The Non-secure Unprivileged Access APB Slave Peripheral Protection Controller Register allows software to configure if each APB peripheral that it controls (by an APB PPC) is Non-secure privileged access only or is also allowed Non-secure Unprivileged access.

Table 3-59 APBNSPPPC0 register

Bits Name Access Reset value Description
[31:5] Reserved RO 0x0 Reserved
4 NS_MHU1 RW 0x0 APB access Non-secure privileged setting for MHU 1
3 NS_MHU0 RW 0x0 APB access Non-secure privileged setting for MHU 0
2 NSP_DTIMER RW 0x0 APB access Non-secure privileged setting for DUAL TIMER
1 NSP_TIMER1 RW 0x0 APB access Non-secure privileged setting for TIMER 1
0 NSP_TIMER0 RW 0x0 APB access Non-secure privileged setting for TIMER 0

Table 3-60 APBNSPPPC1 register

Bits Name Access Reset value Description
[31:1] Reserved RO 0x0 Reserved
0 NSP_S32KTIMER RW 0x0 APB access Non-secure privileged setting for S32KCLK Timer

APBNSPPPCEXP0, APBNSPPPCEXP1, APBNSPPPCEXP2, and APBNSPPPCEXP3

The Expansion Non-secure Privilege Access APB Slave Peripheral Protection Controller Registers 0, 1, 2 and 3 allow software to configure each APB peripheral that it controls from each APB PPC.

Each field defines these conditions for an associated peripheral, by the following settings:

  • 1: Allow Non-secure unprivileged and privileged access.
  • 0: Allow Non-secure privileged access only.

These bits directly control the expansion signals on the Security Control Expansion interface.

All four registers are similar. The bits for register N, where N is from 0-3, are listed in the following table.

Table 3-61 APBNSPPPCEXP<N> register

Bits Name Access Reset value Description
[31:16] Reserved RO 0x0 Reserved
[15:0] APBNSPPPCEXP<N> RW 0x0

Expansion N Non-secure Privilege Access APB slave Peripheral Protection Control. Each bit n drives the output signal APBPPPCEXP<N>[n] if APBNSPPCEXP<N>[n] signal is HIGH, where N is 0-3.

The parameter APBPPCEXP_DIS<N> defines if each bit within this register is implemented so that if APBPPCEXP_DIS<N>[i] = 1, APBNSPPPCEXP<N>[i] is disabled, it reads as zeros, and any writes to it are ignored.

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