A.11 Top-level render time configurations

The SSE-200 provides several render configuration options. You can use these options to control whether the subsystem includes the Crypto element, FPUs, which CMSDK product it uses, and whether to improve timing or reduce latency.

The following table lists the configurable render options.

Table A-27 Configurable render options

Parameter name Default value Description
HAS_CRYPTO 1

Defines whether to include the Crypto element:

0 = Exclude the cryptographic functionality. The render process instantiates a dummy element that provides no cryptographic functionality.

1 = Include the Crypto element, which contains the TrustZone® CryptoCell-312.

See the Arm® CoreLink™ SSE-200 Subsystem for Embedded Release Note for more information about the CC010 CryptoCell bundle name and availability.

BASE_MTX_ZERO_LATENCY_ARBITRATION_EN 0

When a downstream port selects a different upstream port to service, this parameter can add latency:

0 = Inserts one extra clock cycle of latency.

1 = Zero extra clock latency added. With this setting, after a locked transaction, the bus matrix does not insert an IDLE transfer.

Note:

The Arm® AMBA® 5 AHB Protocol Specification recommends that a bus master inserts an IDLE transfer after a locked transfer.
HAS_FPU 1

Defines whether to include the Cortex®-M33 processor FPU in the CPU elements:

0 = Exclude the FPU from the CPU element.

1 = Render the FPU in the CPU element. If you set CPU0_FPU or CPU1_FPU to 1, then you must select this value. See A.8 Top-level parameters for more information about those two Verilog parameters.

See the Arm® CoreLink™ SSE-200 Subsystem for Embedded Release Note for more information about the FPU bundle name.

SRAM_ADDR_WIDTH 15 SRAM bank address width, where the size of each SRAM bank is equal to 2SRAM_ADDR_WIDTH. SRAM_ADDR_WIDTH must be less than or equal to 24 – log2(SRAM_NUM_BANK).
SRAM_NUM_BANK 4

Number of SRAM banks:

  • 1 bank
  • 2 banks
  • 4 banks
  • Others reserved.
CPU0_TYPE 2

CPU 0 core type:

  • 0 = Does not exist
  • 2 = Cortex-M33
  • Others Reserved
CPU1_TYPE 2

CPU 1 core type:

  • 0 = Does not exist
  • 2 = Cortex-M33
  • Others Reserved
NUM_AHBSEXP 2

Number of slave AHB expansion ports:

2 = 2 slave expansion ports.

Others = Reserved.

CPU0_HAS_TCM 0

CPU0 element has a Data TCM:

0 = Not present.

1 = Reserved.

CPU1_HAS_TCM 1

CPU1 element has a Data TCM:

0 = Reserved.

1 = Data TCM is present.

CPU0_TCM_BANK_NUM 0 SRAM bank that maps as CPU 0 TCM. Ignored if CPU 0 has no Data TCM. All Reserved.
CPU1_TCM_BANK_NUM 3 SRAM bank that maps as CPU 1 TCM. Ignored if CPU 1 has no Data TCM.
  • '3'
  • Others Reserved.
SEPARATE_CRYPTO_PD 1

PD_CRYPTO power domain exists:

0 = Reserved.

1 = PD_CRYPTO power domain exists if Crypto element exists.

SEPARATE_CPUDBG_PD 0

PD_CPU<N>CORE and PD_CPU<N>DBG are separate power domains (not merged):

0 = Both PD_CPU<N>CORE and PD_CPU<N>DBG are merged to become PD_CPU<N>CORE. PD_CPU<N>DBG does not exist.

1 = PD_CPU<N>CORE and PD_CPU<N>DBG are separate power domains.

CPU_SYS_RETENTION 0

Remove the retention support:

1 = Retention is supported.

0 = Retention is not supported.

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