3.7 Debug and trace

This section describes the SSE-200 programmable options for debug and trace.

For more information on debug and trace, see the Arm® Cortex®-M33 Processor Technical Reference Manual.

Note:

If the system is configured for CoreSight™ SoC, a license is required for that IP and the following corresponding Arm documentation:

  • Arm® CoreSight™ SoC-400 System Design Guide.
  • Arm® CoreSight™ SoC-400 Technical Reference Manual.
  • Arm® CoreSight™ SoC-400 User Guide.
  • Arm® CoreSight™ DAP-Lite Technical Reference Manual.
This section contains the following subsection:
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