2.7.5 Power Policy Units

The System Control element also provides access to Power Policy Units (PPUs) that are used to control power domains in the system.

All PPUs reside in the always on power domain, PD_AON. The PPUs for CPU0, CPU1, and Debug are reset by nCPUDEBUGPIKRESET. The PPUs for Base, Crypoto and SRAM are reset by nBCRYPTOSPIKRESET. Both resets are synchronized.

The following table lists the configuration of all PPUs in the system.

Note:

M is 0 for CPU 0 and 1 for CPU 1 if it exists, and N represents number(s) between 0 and the number of SRAM Banks minus 1.

Table 2-8 Power Policy Units configurations

PPU configuration PD_SYS PD_CPU <M>CORE PD_CPU <M>DBGa PD_DEBUG PD_SRAM<N> PD_CRYPTO
PPU name SYS_PPU CPU<M>_PPU CPU<M>DBG_PPUa DEBUG_PPU RAM<N>_PPU CRYPTO_PPU
Device interface type P-Channel P-Channel Q-Channela Q-Channel Q-Channel Q-Channel
Default Power Policy (DEF_PWR_POLICY) ON OFFb OFFa ON ON ON
Default Power mode dynamic transition enable (DEF_PWR_DYN_EN) OFF ON ONa OFF OFF OFF
Dynamic support

ON,

FULL_RETc,

OFF

ON,

FULL_RETc,

WARM_RST,

OFF

ONa,

OFFa

ON,

OFF

ON,

MEM_RET

OFF

-
Static support

ON,

FULL_RETdc,

WARM_RSTd,

OFFd

ONd,

FULL_RETdc,

WARM_RSTd,

OFFd

ONa,

WARM_RSTad,

OFFad

ON,

WARM_RSTd,

OFFd

ON,

MEM_RETd,

WARM_RSTd,

OFFd

ON,

WARM_RSTd,

OFF

PWR_MODE_ENTRY_DEL_CFG 0
SW_DEV_DEL_CFG 0
LOCK_CFG 0
MEM_RET_RAM_REG_CFG 0
FULL_RET_RAM_REG_CFG 0
FUNC_RET_RAM_REG_CFG 0
STA_POLICY_PWR_IRQ_CFG 0
STA_POLICY_OP_IRQ_CFG 0
Operating Mode support None

For more details on the PPU, see Arm® Power Policy Unit Architecture Specification, version 1.1.

a If separate CPU debug power domain is not present (when SEPARATE_CPUDBG_PD configuration is False), then this column is invalid. Instead for each core the PD_CPU<M>DBG power domain is merged into the PD_CPU<M>CORE power domain and controlled as if it is just a PD_CPU<M>CORE power domain.
b While the default dynamic power mode of these PPUs is set to OFF, at Cold reset the SSE-200 requests for the processor to powerup depending on the CPUWAIT register values. Warm reset does not depend on CPUWAIT. See 2.9.4 System boot when powering up for more information.
c Logic retention support for both the PD_SYS and PD_CPU<M>CORE are configuration options through the CPU_SYS_RETENTION render configuration. If Logic retention is not supported (when CPU_SYS_RETENTION is 0) then the Dynamic support and Static Support for FULL_RET does not exist.
d The PPU must not be programmed to use static power state because this can cause system deadlocks. And any attempt to write to the PPU_PWPR.OP_DYN_EN register to change to static power mode for each PPU results in a bus error being returned and the write being blocked.
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