A.4.5 Debug APB expansion interface

The following table lists the debug APB expansion interface signals which allow partners to add more debug functionality to the SSE-200.

This interface:

  • Is only accessible from the debug interface using an external DAP.
  • Is synchronous to DEBUGSYSCLK.
  • Is reset using nPORESETDEBUG.
  • Resides in the PD_DEBUG power domain.

Table A-10 Debug APB expansion signals

Signal name Width Direction Clock domain Description
DEBUGPRDATA 32 Input DEBUGSYSCLK APB read data. Drives this bus during read cycles.
DEBUGPREADY 1 Input DEBUGSYSCLK APB ready. Use this signal to extend an APB transfer.
DEBUGPSLVERR 1 Input DEBUGSYSCLK Indicates a transfer failure. The APB peripherals are not required to support the PSLVERR pin.
DEBUGPADDR 30 Output DEBUGSYSCLK The APB address bus for master interface.
DEBUGPSEL 1 Output DEBUGSYSCLK APB select. Indicates that the slave device is selected, and a data transfer is required.
DEBUGPENABLE 1 Output DEBUGSYSCLK APB enable. Indicates the second and subsequent cycles of an APB transfer.
DEBUGPWRITE 1 Output DEBUGSYSCLK APB RW transfer. Indicates an APB write access when HIGH, and an APB read access when LOW.
Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.