2.5.7 Timers and watchdogs

This sections describes the timers and watchdogs in the Base element.

CMSDK APB Timers

The SSE-200 includes two instances of the CMSDK APB timers:

  • CMSDK TIMER 0 in a Non-secure region at 0x4000_0000 and in a Secure region at 0x5000_0000.
  • CMSDK TIMER 1 in a Non-secure region at 0x4000_1000 and in a Secure region at 0x5000_1000.

See the Arm® Cortex®-M System Design Kit Technical Reference Manual.

Dual Timer

The CMSDK APB dual-input timer consists of two programmable 32-bit down-counters that can generate interrupts when they reach zero. The operation of each timer module is identical.

The Base element contains one APB dual-input timer which is located in a Non-secure region at 0x4000_2000 and in a Secure region at 0x5000_2000.

See the Arm® Cortex®-M System Design Kit Technical Reference Manual.

Watchdog timers

The Base element instantiates two APB watchdog timers that are connected to the internal APB bus. Each watchdog is permanently mapped to either a Secure or a Non-secure region of address space:

  • Non-secure CMSDK Watchdog in the Non-secure region at 0x4008_1000.

    The Non-secure Watchdog can raise an interrupt to both processors. On a Watchdog reset request event, a separate interrupt is raised but software can choose to allow it to directly reset the system.

  • Secure CMSDK Watchdog in the Secure region at 0x5008_1000.

    The Secure watchdog can raise a Non-Maskable Interrupt (NMI) to both processors. In this case, a Watchdog reset event resets the entire system.

See the Arm® Cortex®-M System Design Kit Technical Reference Manual.

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