1.4.3 Interrupt controller architecture

The SSE-200 implements the following features:

  • Arm® Nested Vectored Interrupt Controller (NVIC).
  • Arm Wakeup Interrupt Controller (WIC).

See the Arm® Cortex®-M33 Processor Technical Reference Manual for more information on the NVIC. See the Arm® Cortex®-M33 Processor User Guide Reference Material for more information on the WIC.

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