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Up to four SRAM elements can be present. The MPCs in the Base element control security for the SRAM regions.
Up to four MPCs are included, one on each path to a SRAM block, so that accesses can be blocked when a security violation occurs.
Each SRAM block is implemented within an SRAM element. Each MPC APB configuration interface is mapped to the following base addresses:
for SRAM Bank 0.
for SRAM Bank 1.
for SRAM Bank 2.
for SRAM Bank 3.
If any of the SRAM banks do not exist, the associated MPC does not exist and the address area of that MPC is reserved. Any access to it is RAZ/WI.
The cfg_init_value of each MPC is tied LOW so that at boot, the SRAMs are Secure only. Software must change or restore the settings in the MPC to release memory for Non-secure world use.
nWARMRESETSYS resets all SRAM MPCs, which reside in the PD_SYS power domain.
Power management for the SRAM elements is from the PIKs which are controlled from the system control element.