2.9.7 System and processor power states

Each power domain is relatively independent, because of the relationship that is defined in the PDCM and by other request signals. However, it is possible to define several of sensible system level power states that the system as a whole supports.

Table 2-14 System and processor power states

System power state PD_SYS PD_ CPU<N>CORE PD_CPU <N>DBGa PD_ DEBUG PD_ CRYPTO PD_ SRAM<N> Main clockb
OFF OFF OFFc OFF OFF OFF OFF OFF
HIBERNATION OFF OFFd OFF OFF/ON OFF OFF/ MEM_RET OFF/ONe
OFF – DEEPSLEEP WITH WIC + EWC
SYS_RETg RETg OFFf OFF OFF/ON OFF OFF/ MEM_RET ON
OFF – DEEPSLEEP WITH WIC + EWC
RETg – DEEPSLEEP WITH WIC
SYS_ON ON OFFf OFF OFF/ON OFF/ON ON/OFF/ MEM_RET ON
OFF – DEEPSLEEP WITH WIC + EWC
RETgh – DEEPSLEEP WITH WIC
ON - DEEPSLEEP WITH WIC ON/OFF
ON - SLEEP
ON

Note:

All domains, including the PD_SYS and PD_CPU<N>CORE power domains, are independent power domains with relationships that are enforced by the PDCM.

When any PD_CPU<N>CORE is turned ON, the PD_SYS also turns ON. PD_SYS might take longer to turn ON compared to the CPU, therefore the system might be in a temporary state where the PD_SYS is OFF while PD_CPU<N>CORE is ON.

The implementer must ensure that during physical implementation this is considered, especially when dealing with signal isolation.

a The PD_CPU<N>DBG column is not used if there is no support for separate processor debug power domain (if SEPARATE_CPUDBG_PD configuration is False).
b Main clock is active as requested by the subsystem. Execute activity request with the EXPCLKREQ and EXPCLKRDY signals.
c All CPUs must be OFF.
d This entry is similar to footnote f except that at least one core is expected to be in OFF – DEEPSLEEP WITH WIC + EWC state. If all cores are in the OFF state without enabling EWC, then expansion hardware must request the system to power up using the PD_SYS Power Control Q-Channel interface or using the GPR of the Debug element.
e When in HIBERNATION state, if PD_DEBUG is ON, then MAINCLK is running. Otherwise MAINCLK is OFF.
f These entries allow one or more of the processors to be turned off and not used. A processor in this state cannot be woken using its interrupts and instead can only be woken by the PDCM, or by another entity writing to the PPU for the processor if the system is in the SYS_ON state.
g Logic Retention support for PD_SYS and PD_CPU<M>CORE are configuration options through the CPU_SYS_RETENTION render configuration. If logic retention is not supported, SYS_RET System Power State does not exist, and RET– DeepSleep with WIC power state of any of the PD_CPU<N>CORE does not exist either.
h If Logic Retention is not supported (when CPU_SYS_RETENTION configuration = 0), any attempt to enter this state, and therefore enter retention with the processor, results in the processor remaining ON, giving the impression that the processor state is still being retained.
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