2.3.4 Processor reset handling

Because the Cortex®-M33 core normally handles reset on its own, nPORESETAON is fed directly to the Cortex-M33 core. nSYSRESET of the Cortex-M33 core is generated from the local PPU as the PPU can handle Warm reset of the core.

The reset from the PPU, DEVRETRESETn, is combined with S32KCLK synchronized and locked nSRST to hold the core in reset until nSRST is deasserted. This allows a debugger to hold the processor core in reset while it uses the Debug Access Port to perform debug operations.

Boot after reset

After reset, both processors boot the instruction at the boot address from the vector offset address register in the System Control Registers.

Note:

  • Static top-level configuration parameters determine the contents of the vector offset address register in the System Control Registers. The default address is 0x00000000 and is statically mapped to code memory of the AHB Master Expansion Code interface.
  • Software can modify the boot addresses before a warm reboot of the processors.
  • See A.6.2 Top-level static configuration signals and the Arm® CoreLink™ SSE-200 Subsystem for Embedded Configuration and Integration Manual.

The TrustZone® for Armv8-M requirement for boot up is that execution starts from a Secure memory space, and optionally automatically executes Non-secure firmware after Secure world initialization. At boot, the SRAM is Secure only. Software must change or restore the settings in the MPC to release memory for Non-secure world use.

The CPUWAIT input of the CPU can force the Cortex-M33 processor to wait before executing the instruction. Each processor in the system has an associated CPU_WAIT register that controls, if it starts running boot code when it wakes.

See the Arm® Cortex®-M33 Processor Technical Reference Manual.

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