2.3.2 Reset inputs and outputs

The following reset-related signals in the subsystem are from or to the AON part of the subsystem:

This is the Power-on reset input for the SSE-200. Arm recommends that this signal is one or more S32CLK cycles long.

This signal, typically from an external debugger, is the system-wide Cold reset request:

  • This reset is applied to the subsystem on the falling edge of the nSRST signal and then removed, except for the nSYSRESET pin of each processor core.
  • If nSRST is held low, all processor cores are also stopped from booting.

The nSRST input must be a minimum of three S32KCLK cycles long. nSRST can be held LOW while performing other debug related tasks to indefinitely prevent the processor from execution. This might be done, for example, when inserting a debug certificate into the SRAM. When nSRST is deasserted, it must be held inactive for at least three S32KCLK cycles before being asserted again.


This signal performs the Warm reset of the system. It is the reset source for all Warm resets synchronized to local clocks. This signal:

  • Must not be used to reset any debug-related logic.
  • Is also asserted if nPORESETAON is asserted.
  • Is a superset of system Cold reset (see 2.3.5 nWARMRESETAON).
  • Is asynchronous and must be resynchronized before use.

This signal performs the Cold reset of the system. This is the reset source for all Cold resets synchronized to the local clocks. This signal:

  • Is also asserted if nPORESET is asserted.
  • Is a superset of Power-on reset (see 2.3.3 nPORESET handling).
  • Is asynchronous and must be resynchronized before use.


This allows external expansion logic to request a system reset:

  • After it is asserted, the signal must be held HIGH until the reset occurs on nPORESETAON.
  • The signal must be cleared because of the assertion of nPORESETAON.
The EXPWARMRESETREQ expansion Warm reset output signal, when set to HIGH, indicates that the reset logic is about to assert a Warm reset to the system. This waits for the EXPWARMRESETACK signal to be HIGH before asserting the reset, allowing any external logic to complete critical operations by delaying the assertion of Warm reset.



The EXPWARMRESETACK expansion Warm reset input signal works along with EXPWARMRESETREQ, allowing external logic to delay the assertion of Warm reset.

The following signals are provided for expansion of other power domains in the subsystem:


This is the system reset signal for expansion logic in the PD_SYS power domain.

It supports logic retention and is not asserted if the PD_SYS power domain is entering retention state.

This is the Power-on reset signal for debug expansion logic in the PD_DEBUG power domain.
This is the Crypto element active LOW, Warm reset output signal. This output only exists if the Crypto element exists.
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