3.4.1 CMSDK timer

The base element has two CMSDK Timers:

  • CMSDK TIMER 0 is located in a Non-secure region at 0x4000_0000 and in a Secure region at 0x5000_0000.
  • CMSDK TIMER 1 is located in a Non-secure region at 0x4000_1000 and in a Secure region at 0x5000_1000.


CTI triggers from the debug subsystem halt the timer.

The EXTIN input of the timers is connected to the CTI debug halt logic, and it is used to stop the timer counter logic, if there is a debug halt access.

To enable this functionality the EXTIN must be enabled by writing to the CTRL register:

  • CTRL bit[2] = 0.

  • CTRL bit[1] = 1.

nWARMRESETSYS resets the timer, which resides in the PD_SYS power domain.

The following table lists a summary of the registers in the timer.

Table 3-20 Summary of CMSDK Timer registers

Offset Name Access Width Reset value Description
0x000 CTRL RW 4 0x0

3: Interrupt enable.

2: Select external input as clock.

1: Select external input as enable.

0: Enable.

0x004 VALUE RW 32 0x0 Current value.
0x008 RELOAD RW 32 0x0 Reload value. A write to this register sets the current value.



RW 1 0x0

Timer interrupt.

Write 1 to clear.

0xFD0 PID4 RO 8 0x04 Peripheral ID register 4.
0xFD4 PID5 RO 8 0x0 Peripheral ID register 5.
0xFD8 PID6 RO 8 0x0 Peripheral ID register 6.
0xFDC PID7 RO 8 0x0 Peripheral ID register 7.
0xFE0 PID0 RO 8 0x22

Peripheral ID register 0.

[7:0]: Part number[7:0].

0xFE4 PID1 RO 8 0xB8

Peripheral ID register 1.

[7:4]: jep106_id_3_0.

[3:0]: Part number[11:8].

0xFE8 PID2 RO 8 0x0B

Peripheral ID register 2.

[7:4]: Revision.

[3]: jedec_used.

[2:0]: jep106_id_6_4.

0xFEC PID3 RO 8 0x0

Peripheral ID register 3

[7:4]: ECO revision number.

[3:0]: Customer modification number.

0xFF0 CID0 RO 8 0x0D Component ID register 0.
0xFF4 CID1 RO 8 0xF0 Component ID register 1.
0xFF8 CID2 RO 8 0x05 Component ID register 2.
0xFFC CID3 RO 8 0xB1 Component ID register 3.

See the Arm® Cortex®-M System Design Kit Technical Reference Manual for register details.

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