3.2.2 SRAM overview

The subsystem supports four SRAM elements.

All SRAMs are of the same size and all SRAMs form a contiguous area of memory. Collectively they are mapped into both the Secure and Non-secure regions. The remainder of the regions are reserved. A memory protection controller then determines how the memory locations within the SRAM are mapped to the Secure and Non-secure regions.

The following table shows a configuration of four memory banks of 32KB each.

Table 3-2 Internal SRAM regions

ID (alias) Address   Size Region name Description Security
  From To        
1 (6) 0x2000_0000 0x2000_7FFF 32KB SRAM Bank 0 Maps to Internal SRAM Bank 0. NS-MPC
2 (7) 0x2000_8000 0x2000_FFFF 32KB SRAM Bank 1 Maps to Internal SRAM Bank 1. NS-MPC
3 (8) 0x2001_0000 0x2001_7FFF 32KB SRAM Bank 2 Maps to Internal SRAM Bank 2. NS-MPC
4 (9) 0x2001_8000 0x2001_FFFF 32KB SRAM Bank 3 Maps to Internal SRAM Bank 3. NS-MPC
5 0x2002_0000 0x20FF_FFFF - Reserved Reserved. -
6 (1) 0x3000_0000 0x3000_7FFF 32KB SRAM Bank 0 Maps to Internal SRAM Bank 0. S-MPC
7 (2) 0x3000_8000 0x3000_FFFF 32KB SRAM Bank 1 Maps to Internal SRAM Bank 1. S-MPC
8 (3) 0x3001_0000 0x3001_7FFF 32KB SRAM Bank 2 Maps to Internal SRAM Bank 2. S-MPC
9 (4) 0x3001_8000 0x3001_FFFF 32KB SRAM Bank 3 Maps to Internal SRAM Bank 3. S-MPC
10 0x3002_0000 0x30FF_FFFF - Reserved Reserved. -

Note:

  • For NS-MPC, any Secure access targeting this region is blocked. An MPC controls Non-secure access to this region.
  • For S-MPC, any Non-secure access targeting this region is blocked. An MPC controls Secure access targeting this region.
Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.