2.7.3 Timers and watchdogs

The SSE-200 implements a single CMSDK Timer and a single CMSDK Watchdog that run on S32KCLK.

The timer is aliased onto Secure and Non-secure regions. The watchdog is permanentley mapped to the Secure region. The System Control element APB Peripherals Protection Controller controls the region that the timer resides in. The timer can raise an interrupt to both processor cores and the watchdog timer can raise a Non-Maskable Interrupt to both processor cores. When the Watchdog reset event occurs, it resets the entire system. See 2.3 Resets.

The timer and watchdog can be halted using CTI triggers from the debug subsystem. See 2.8 Debug element.

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