2.2.1 Overview

The following clocks are present in the SSE-200:

All derived clocks are synchronous to the main input clock and a range of primary to secondary ratios are supported.

The generated clocks are locally clock gated within each element depending on which reset domain it is on, and the activity and power state of the dependent logic. The power state of dependent logic is controlled by the related Power Policy Unit (PPU). Some of the gated clocks are output for expansion logic in the same clock, reset, and power domains.

The following diagram shows the interconnections for the clock signals:

In the diagram:

Figure 2-2 Clock interconnection
To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

The Clock Request Controller handshakes with the external clock generator to turn off the main clock when it is not required.

System control registers control the clock dividers.

Q-Channel based clock control logic provides the following features:

Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.