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The following clocks are present in the SSE-200:
The subsystem uses the clock MAINCLK input to derive:
SYSCLK which is the clock for the primary processor, bus matrix, most of the SRAMs, and peripherals.
FCLK is used by the debug system, secondary processor, and the last SRAM.
SRAM element 3 is also used for Tightly Coupled Memory (TCM) to provide higher performance for data accesses.
A slow clock is used by some modules within the system control element.
The S32KCLK clock is an asynchronous clock input that is used primarily to drive the S32KWATCHDOG. S32KCLK also drives the S32KTIMER, and other logic that must be clocked at the lowest system power mode (hibernation).
All derived clocks are synchronous to the main input clock and a range of primary to secondary ratios are supported.
The generated clocks are locally clock gated within each element depending on which reset domain it is on, and the activity and power state of the dependent logic. The power state of dependent logic is controlled by the related Power Policy Unit (PPU). Some of the gated clocks are output for expansion logic in the same clock, reset, and power domains.
The following diagram shows the interconnections for the clock signals:
In the diagram:
The Clock Request Controller handshakes with the external clock generator to turn off the main clock when it is not required.
System control registers control the clock dividers.
Q-Channel based clock control logic provides the following features: