3.2.3 Processor overview

This section describes memory and registers associated with the Cortex®-M33 processors.

Private CPU regions

Each of the two processor elements in the SSE-200 can only see its own implementation of the Private CPU Region within the CPU element.

This region consists of a Secure region from 0x4001_000-0x4001_FFFF, and a Non-secure region from 0x5001_0000-0x05001_FFFF, as shown in the following table.

Table 3-3 Private core regions

ID (alias) Address Size Region name Description Security
  From To        
- 0x4001_0000 0x4001_EFFF - Reserved Reserved. -
1 (4) 0x4001_F000 0x4001_FFFF 4KB CPU_IDENTITY CPU Identity Unit. NS
2 0x5001_0000 0x5001_0FFF 4KB ICACHE Local instruction cache. SP
3 0x5001_1000 0x5001_1FFF 4KB CPUSECCTRL CPU Local Security Control. SP
- 0x5001_2000 0x5001_EFFF - Reserved Reserved. -
4 (1) 0x5001_F000 0x5001_FFFF 4KB CPU_IDENTITY CPU Identity Unit. S

Note:

  • These regions are not accessible from any other master in the system, including the expansion slave interfaces. An external debugger can however access the regions through the Debug AHB access interface.
  • Only 32-bit writes are supported.
  • NS indicates Non-secure access only.
  • SP indicates Secure privilege access only.
  • S indicates Secure access only.
  • For CPU_IDENTITY, both Secure and Non-secure areas are always accessible. Any write access to it is ignored.

PPB regions

The Private Peripheral Bus (PPB) provides access to the internal processor resources.

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