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For each processor to enter a lower power state, the processor must enter SLEEP or DEEPSLEEP state.
When entering DEEPSLEEP, different combinations of WIC and EWC first enable, and then determine, the different processor power state being entered. The following shows the key power states of the processor that the subsystem supports:
When the PD_CPU<N>CORE is entering the OFF – DEEPSLEEP with WIC + EWC state from the ON state, the processor must first enable its WIC, followed by handshaking to enable its associated EWC, then enabling DEEPSLEEP before entering WFI.
This is the only state that actually supports processor power being fully turned off with the ability to wake the core from interrupts.
When the PD_CPU<N>CORE is entering the RET – DeepSleep with WIC or ON – DeepSleep with WIC from the ON state, the processor must first enable its WIC, then enable DeepSleep before entering WFI.
DEEPSLEEP WITH WIC can only support the core in retention, or ON with simply the core and NVIC clock turned OFF.
When the PD_CPU<N>CORE is entering the OFF state, WIC and EWC are not enabled. Enable DeepSleep before the processor enters WFI.
OFF state means that the processor cannot be woken from interrupts, and the only way to wake the processor is by writing to the PPUs to manually turn it ON.
When the PD_CPU<N>CORE power domain is entering the ON – SLEEP state from the ON state, the processor at entering WFI has disabled DeepSleep.
When in ON – Sleep, the processor is still ON and the NVIC is clocking with the rest of the core clock turned off.
Because the FPU is now part of the processor main core power domain, before the processor is able to enter an OFF state, the FPU must be made unavailable by both setting the CP10 field of the CPACR Register in the processor to
0b00 and setting the SU10 field of CPPWR Register in the processor to 1.