3.4.3 CMSDK watchdog timers

The Base element has two CMSDK watchdog timers:

  • The Non-secure CMSDK watchdog is in the Non-secure region at 0x4008_1000
  • The Secure CMSDK watchdog is in the Secure region at 0x5008_1000

Each watchdog is permanently mapped to either a Secure or a Non-secure region of address space:

  • The Non-secure watchdog can raise an interrupt to both cores. On a Watchdog reset request event, a separate interrupt is raised instead, but software can also choose to allow it to directly reset the system.
  • The Secure Watchdog can raise a Non-Maskable Interrupt (NMI) to both cores. However, in this case, a Watchdog reset event resets the entire system.

CTI triggers from the debug subsystem halt the timers.

nWARMRESETSYS resets the timers, which reside in the PD_SYS power domain.

The following table shows a summary of the CMSDK watchdog registers.

Table 3-22 Summary of Watchdog registers

Offset Name Access Width Reset value Description
0x00 WDOGLOAD RW 32 0xFFFFFFFF Contains the value from which the counter is to decrement.
0x04 WDOGVALUE RO 32 0xFFFFFFFF Contains the current value of the decrementing counter.
0x08 WDOGCONTROL RW 2 0x0 Enables the software to control the watchdog unit.
0x0C WDOGINTCLR WO - - A write of any value register clears the watchdog interrupt, and reloads the counter from the value in WDOGLOAD.
0x10 WDOGRIS RO 1 0x0 Indicates the raw interrupt status from the counter.
0x14 WDOGMIS RO 1 0x0 Indicates the masked interrupt status from the counter.
0xC00 WDOGLOCK RW 32 0x0 Disables write accesses to all other registers.
0xF00 WDOGITCR RW 1 0x0 Enables integration test mode.
0xF04 WDOGITOP WO 2 0x0 When the WDOGITOP Register is in integration test mode, the values in this register directly drive the enabled interrupt output and reset output.
0xFD0 WDOGPERIPHID4 RO 8 0x04

Peripheral ID Register 4:

Bits[7:4]: Block count.

Bits[3:0]: jep106_c_code.

0xFD4 WDOGPERIPHID5 RO 8 0x0 Peripheral ID Register 5.
0xFD8 WDOGPERIPHID6 RO 8 0x0 Peripheral ID Register 6.
0xFDC WDOGPERIPHID7 RO 8 0x0 Peripheral ID Register 7.
0xFE0 WDOGPERIPHID0 RO 8 0x24

Peripheral ID Register 0:

Bits[7:0]: Part number[7:0].

0xFE4 WDOGPERIPHID1 RO 8 0xB8

Peripheral ID Register 1:

Bits[7:4]: jep106_id_3_0.

Bits[3:0]: Part number[11:8].

0xFE8 WDOGPERIPHID2 RO 8 0x1B

Peripheral ID Register 2:

Bits[7:4]: Revision.

Bit[3]: jedec_used.

Bits[2:0]: jep106_id_6_4.

0xFEC WDOGPERIPHID3 RO 8 0x0

Peripheral ID Register 3:

Bits[7:4]: ECO revision number.

Bits[3:0]: Customer modification number.

0xFF0 WDOGPCELLID0 RO 8 0x0D Component ID Register 0.
0xFF4 WDOGPCELLID1 RO 8 0xF0 Component ID Register 1.
0xFF8 WDOGPCELLID2 RO 8 0x05 Component ID Register 2.
0xFFC WDOGPCELLID3 RO 8 0xB1 Component ID Register 3.

See the Arm® Cortex®-M System Design Kit Technical Reference Manual for register details of the watchdog timer.

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