B.1 Revisions

This appendix describes technical changes between released issues of this book.

Table B-1 Issue A

Change Location Affects
First release - -

Table B-2 Differences between issue A and issue 0100-00

Change Location Affects
Numerous minor technical updates applied throughout document. All sections r1p0 EAC release
Added Warm reset signal information. 2.3.2 Reset inputs and outputs r1p0 EAC release
Added PPU description to Resets section. 2.3.5 nWARMRESETAON r1p0 EAC release
Multiple changes to processor configuration option.s 2.4 CPU elements r1p0 EAC release
Debug and Certificate access updates. Certificate Access r1p0 EAC release
Memory map figure and notes updated. 3.2.1 Memory map overview r1p0 EAC release
CPU_IDENTIY register block section added to CPU element chapter. 3.3.5 CPU_IDENTITY r1p0 EAC release
Interrupt signals updated. A.2 Interrupt signals r1p0 EAC release
New section added to Appendix: Top-level parameters. A.8 Top-level parameters r1p0 EAC release
New section added to Appendix: Top-level render time configurations. A.11 Top-level render time configurations r1p0 EAC release

Table B-3 Differences between issue 0100-00 and issue 0200-00

Change Location Affects
MHU feature description updated. 1.2 Features of the SSE-200 All revisions
Removed listings from SIE-200 components: AHB5 to APB4 Asynchronous Bridge; Power Dependency Control Matrix. 1.3 CoreLink SIE-200 components All revisions
Added references. 1.4.2 Debug All revisions
Signal names updated in figure. Figure   2-2 Clock interconnection All revisions
Signal names for clock generation and control updated. 2.2.2 Clock generation and control All revisions
SRAM element and Crypto element descriptions updated. 2.2.5 Component clocks All revisions
Figure updated. Figure   2-3 Reset interconnection All revisions
Update to reset signal descriptions for: nSRST, nWARMRESETAON, nPORESETAON. Added reset signal nWARMRESETCRYPTO . 2.3.2 Reset inputs and outputs All revisions
Registers added to description for nWARMRESETAON. 2.3.5 nWARMRESETAON All revisions
CPU 0/1 default values clarified for IRQDIS parameter. 2.4.2 Cortex-M33 configurations All revisions

Section updated for INVMAT description, instruction cache DMA parameter and REDUCE_READS.

2.4.3 Instruction cache All revisions
External WIC Wake support column added to table. Table   2-4 Interrupt sources All revisions
Renamed section: AHB5 TrustZone peripheral protection controller now called APB TrustZone peripheral protection controller. 2.5.5 APB TrustZone peripheral protection controller All revisions
Section update: reference to AHB5 master expansion code removed. 2.5.8 Expansion ports All revisions
Feature description of SRAM banks updated. 2.6.2 SRAM banks All revisions
Reset signals for PPUs in subsystem elements described and table footnotes updated. 2.7.5 Power Policy Units All revisions
PD_CRYPTO power domain map updated in figure. Figure   2-8 SSE-200 power domains All revisions
Section update and Note added - resets and power ups clarified. 2.9.4 System boot when powering up All revisions
Section update - interrupt parameters clarified. 2.9.5 External wakeup controllers All revisions
Section update. 2.9.8 Entering lower processor power states All revisions
Note added. 2.9.9 Hibernation All revisions

Figure and table update - address ranges updated for reserved memory regions.

Figure   3-1 SSE-200 Simplified view memory map All revisions
Table update - address ranges updated for CryptoCell and reserved regions of memory (ID8 and 9). 3.2.4 Base peripheral overview All revisions
Section updates:
  • Table updates - reset values and descriptions updated for INVMAT, DMA and STATS in Base peripheral overview
  • Table updates - reserved bits updated; added POINV_SMP sample value in ICCTRL register
  • Performance targets and Cache misses description updated in Processor L1 cache programming
  • Description and task steps updated in Ensuring the cache handles memory modifications
  • Table update - PIDR5,6,7 registers changed to Reserved in CPU Local Security Control Register
  • Table updates - IRQ[8]and[20] changed from Reserved to CryptoCell; Debug IRQ[18-19] changed to optional in Interrupts.
3.3 CPU element All revisions
Register table updates:
  • BUSWAIT register, SECPPCINTEN register, APBNSPPC1 register, NSMSCEXP register
  • SECDBGSTAT register, SECDBGSET register, SECDBGCLR register, SCSECCTRL register, CLOCK_FORCE register.
3.4 Base element All revisions
Table removed - Summary of PPU registers removed (replaced by reference to architecture document) 3.6.5 Power Policy Unit registers All revisions
Description updated. 3.7 Debug and trace All revisions
Reset signal name changed: nPORESETDBG changed to nPORESETDEBUG. A.1.1 Functional clock and reset signals All revisions
Description updated. A.1.2 Clock control Q-Channel signals All revisions
Signals added - HREADYMUX and CODEEXPHREADYMUX A.3 AHB expansion bus signals All revisions
Table descriptions updated. A.8 Top-level parameters All revisions
Added section. A.9 Security control expansion parameters All revisions
Added section. A.10 Interrupt parameters All revisions
Table update - descriptions of parameters updated. A.11 Top-level render time configurations All revisions
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