There are two Cortex®-M33 cores in the SSE-200:
- The primary core in the CPU0 element is synchronous to the main interconnect and runs the operating system.
- The secondary core in the CPU1 element by default assumes an FPU and DSP. It is synchronous to the main clock, but runs
N times faster.
The Cortex-M33 processor has the
- Three-stage pipeline.
- ARMv8-M Mainline profile.
- TrustZone® for Armv8-M security.
- Up to eight SAU entries each (configurable).
- Up to 16 MPU regions with eight Secure and eight Non-secure (configurable).
- IDAU defining high-level security memory mapping.
has configuration parameters that can be set in the design stage to specify the processor
- If the FPU is present.
- If the Digital Signal Processing extension instructions
- If the coprocessor interface is present.
- The number of Non-secure and Secure MPU regions.
- The number of security attribution unit regions.
- The number of user interrupts.
- The interrupt priority and interrupt
latency that is
- Debug resources and trace support.
See 2.4.2 Cortex-M33 configurations and the Arm® CoreLink™ SSE-200 Subsystem for Embedded Configuration and Integration Manual for more details on system configuration options.
The following figure shows a block diagram of the Cortex-M33 processor logic and CoreSight™ SoC interface: