2.4.5 Interrupts

The CPU element provides the following events that can generate interrupts in the system:

  • Instruction cache IRQ.
  • PPU0/PPU1 IRQ.
  • Cross Trigger Interface (CTI) IRQ [1:0].

In addition to the interrupts, the following events can be used to control instruction execution:

  • RXEV (incoming event) is the event that is received by the Cortex®‑M33 processor and is connected to the TXEV of the other processor in the system.
  • TXEV (outgoing event) is the event that is transmitted by Cortex‑M33 processor and is connected to the RXEV of the other processor in the system.

The following table shows the interrupt sources for CPU0 and CPU1, and it shows which interrupt acts as a wakeup for the associated external WIC of each processor.

Table 2-4 Interrupt sources

Interrupt Input CPU 0 and CPU 1 interrupt source External WIC Wake support
NMI Combined Secure Watchdog, S32kwatchdog, and NMI_Expansion Yes
IRQ[0] Non-secure Watchdog reset Request Yes
IRQ[1] Non-secure Watchdog Interrupt Yes
IRQ[2] S32K Timer Yes
IRQ[3] Timer 0 Yes
IRQ[4] Timer 1 Yes
IRQ[5] Dual Timer Yes
IRQ[6] Message Handling Unit 0 CPUn Interrupt Yes
IRQ[7] Message Handling Unit 1 CPUn Interrupt Yes
IRQ[8] CryptoCell-312 (if CryptoCell is present) Yes
IRQ[9] MPC Combined (Secure) Yes
IRQ[10] PPC Combined (Secure) Yes
IRQ[11] MSC Combined (Secure) Yes
IRQ[12] Bridge Error Combined Interrupt (Secure) Yes
IRQ[13] CPUn instruction cache Interrupt No
IRQ[14] Reserved -
IRQ[15] SYS_PPU No
IRQ[16] CPU0_PPU No
IRQ[17] CPU1_PPU No
IRQ[18] CPU0DBG_PPU (if SEPARATE_CPUDBG_PD configuration is True) No
IRQ[19] CPU1CBG_PPU (if SEPARATE_CPUDBG_PD configuration is True) No
IRQ[20] Crypto PPU (if CryptoCell is present) No
IRQ[21] Reserved -
IRQ[22] RAM0_PPU No
IRQ[23] RAM1_PPU No
IRQ[24] RAM2_PPU No
IRQ[25] RAM3_PPU No
IRQ[26] DEBUG_PPU No
IRQ[27] Reserved -
IRQ[28] CPUnCTIIRQ0 No
IRQ[29] CPUnCTIIRQ1 No
IRQ[30] Reserved -
IRQ[31] Reserved -
IRQ[95:32] Expansion Interrupt Inputs. Configurable

Note:

  • Unless specified, both cores receive the same interrupt signals.
  • Each processor only sees its own local instruction cache interrupt and CTIIRQ interrupts. Instruction cache and all PPUs interrupts must be handled as Secure interrupts.
  • If, because of the system configuration, an interrupt source does not exist, the unused interrupt pin is not used, and the interrupt is disabled and reserved.

The Non-secure watchdog interrupt signal and its reset request signal are both used to generate interrupts to the processor. The reset request interrupt must be handled as a Secure interrupt by the Trusted Execution Environment (TEE) so that it does not directly reset the system. To enable the Non-secure Watchdog reset of the system, set the NSWD_EN field in the RESET_MASK register to HIGH.

The Secure watchdog interrupt request and the S32K Watchdog interrupt request are merged to generate an internal NMI. This interrupt can be used to raise an NMI interrupt on CPU0 or CPU1.

The settings in the NMI_ENABLE register can be modified to allow software to route the watchdog interrupts to a single core. That core can then own the interrupt handling for the watchdog interrupt.

The NMI_ENABLE register has masks for the expansion external NMI interrupt inputs to allow software to determine if the external NMI must be raised. These interrupts must all be handled as Secure interrupts.

There are two Message Handling Units (MHUs) in the system. If the system supports a Trusted Execution Environment (TEE), one MHU must be configured as a Secure MHU and the other as a Non-secure MHU.

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