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This section describes the SRAM-related features of the base element.
The MPCs in the base element control the security for the SRAM regions.
One Memory Protection Controller (MPC) is included on the path to each SRAM block so that accesses can be blocked when a security violation occurs.
Each SRAM block is implemented within an SRAM element. Each MPC APB configuration interface is mapped to the following base addresses:
for SRAM Bank 0.
for SRAM Bank 1.
for SRAM Bank 2.
for SRAM Bank 3.
cfg_init_value of each MPC is tied
to 0 so that at boot, the SRAM is Secure only. Software must change
or restore the settings in the MPC to release memory for Non-secure
The BLK_SIZE configuration of each MPC, which defines the MPC block size, is defined by the top-level parameter SRAM_MPC_BLK_SIZE. This is set at a default value of 3 to select 256 byte blocks.
The GATE_PRESENT configuration parameter of each MPC is set to 0 to disable the MPC gating feature.
All SRAM MPCs reside in the PD_SYS power domain and are reset by nWARMRESETSYS.
The AHB5 fabric is designed to keep an SRAM element, SRAM Bank 3, close to the secondary core, and for both to run at a higher clock speed. This allows the SRAM to function as Tightly-Coupled Memory (TCM) on the secondary processor data bus.