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There are four banks of contiguous SRAM. Each SRAM element has the following features:
The last bank of SRAM is the Data Tightly Coupled Memory (DTCM) that provides high throughput for the secondary core because it is tightly integrated and runs at the same speed.
Each SRAM Element resides in the PD_SRAM<N> power domain and generates its own reset from nWARMRESETAON.