2.6.2 SRAM banks

There are four banks of contiguous SRAM. Each SRAM element has the following features:

  • Configurable amount of SRAM memory as long as:
    • The size of each is a power of 2.
    • The total memory size of all four SRAM banks combined is less than 16Mbytes.
    • Minimum SRAM size is 1Kbyte.
    • All SRAM sizes are the same.
  • CoreLink SIE-200 AHB5 SRAM Interface.
  • Exclusive Access Monitor (EAM).


Each SRAM Element has a memory protection controller associated with it and is implemented within the Base element.

The last bank of SRAM is the Data Tightly Coupled Memory (DTCM) that provides high throughput for the secondary core because it is tightly integrated and runs at the same speed.

Each SRAM Element resides in the PD_SRAM<N> power domain and generates its own reset from nWARMRESETAON.

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