3.3.7 Interrupts

This section describes the (Nested Vectored Interrupt Controller) NVIC and the interrupt signal map.

The NVIC supports:

  • An implementation-defined number of interrupts in the range 4-480.
  • A programmable priority level of 0-255 for each interrupt. A higher level corresponds to a lower priority, so level 0 is the highest interrupt priority.
  • Level and pulse detection of interrupt signals.
  • Dynamic reprioritization of interrupts.
  • Grouping of priority values into group priority and subpriority fields.
  • Interrupt tail-chaining.
  • An external Non-Maskable Interrupt (NMI)
  • Optional External Wake Up Controllers that provide ultra-low power sleep mode support.

Interrupt signals

This section describes interrupt signals and exceptions.

Table 3-18 Interrupt signals

Interrupt input CPU 0 interrupt source CPU 1 interrupt source
NMI Combined SECURE WATCHDOG, S32KWATCHDOG, and NMI_Expansion Combined SECURE WATCHDOG, S32KWATCHDOG, and NMI_Expansion.
IRQ[0] NON-SECURE WATCHDOG Reset Request NON-SECURE WATCHDOG Reset Request.
IRQ[1] NON-SECURE WATCHDOG Interrupt NON-SECURE WATCHDOG Interrupt.
IRQ[2] S32K Timer S32K Timer.
IRQ[3] TIMER 0 TIMER 0.
IRQ[4] TIMER 1 TIMER 1.
IRQ[5] DUAL TIMER DUAL TIMER.
IRQ[6] Message Handling Unit 0 CPU0 Interrupt Message Handling Unit 0 CPU1 Interrupt.
IRQ[7] Message Handling Unit 1 CPU0 Interrupt Message Handling Unit 1 CPU1 Interrupt.
IRQ[8] CryptoCell-312 CryptoCell-312.
IRQ[9] MPC Combined (Secure) MPC Combined (Secure).
IRQ[10] PPC Combined (Secure) PPC Combined (Secure).
IRQ[11] MSC Combined (Secure) MSC Combined (Secure).
IRQ[12] Bridge Error Combined Interrupt (Secure) Bridge Error Combined Interrupt (Secure).
IRQ[13] CPU 0 Instruction Cache Interrupt CPU 1 Instruction Cache Interrupt.
IRQ[14] Reserved Reserved.
IRQ[15] SYS_PPU SYS_PPU.
IRQ[16] CPU0_PPU CPU0_PPU.
IRQ[17] CPU1_PPU CPU1_PPU.
IRQ[18] CPU0DBG_PPU (Optional) CPU0DBG_PPU (Optional).
IRQ[19] CPU1DBG_PPU (Optional) CPU1DBG_PPU (Optional).
IRQ[20] CRYPTO_PPU (Optional) CRYPTO_PPU (Optional).
IRQ[21] Reserved Reserved.
IRQ[22] RAM0_PPU RAM0_PPU.
IRQ[23] RAM1_PPU RAM1_PPU.
IRQ[24] RAM2_PPU RAM2_PPU.
IRQ[25] RAM3_PPU RAM3_PPU.
IRQ[26] DEBUG_PPU DEBUG_PPU.
IRQ[27] Reserved Reserved.
IRQ[28] CPU0CTIIRQ0 CPU1CTIIRQ0.
IRQ[29] CPU0CTIIRQ1 CPU1CTIIRQ1.
IRQ[31:30] Reserved Reserved.
IRQ[95:32] Expansion Interrupt Inputs Expansion Interrupt Inputs.

Interrupt controller registers

A summary of the interrupt controller registers is listed in the following table.

Table 3-19 Summary of interrupt controller registers

Address Name Access Reset value Description
0xE000E004 ICTR RO - Interrupt Controller Type Register.
0xE000E1000xE000E11C NVIC_ISER0-NVIC_ISER7 RW 0 Interrupt Set Enable Registers.
0xE000E1800xE000E19C NVIC_ICER0-NVIC_ICER7 RW 0 Interrupt Clear Enable Registers.
0xE000E2000xE000E21C NVIC_ISPR0-NVIC_ISPR7 RW 0 Interrupt Set Pending Registers.
0xE000E2800xE000E29C NVIC_ICPR0-NVIC_ICPR7 RW 0 Interrupt Clear Pending Registers.
0xE000E3000xE000E31C NVIC_IABR0-NVIC_IABR7 RO 0 Interrupt Active Bit Registers.
0xE000E4000xE000E41F NVIC_IPRO-NVIC_IPR7 RW 0 Interrupt Priority Registers.

For more information on the interrupt controller, see the following documents:

  • Arm® Cortex®-M33 Processor Technical Reference Manual.
  • Arm®v8-M Architecture Reference Manual.
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