3.2.4 Base peripheral overview

The base peripheral region is where most peripherals within the subsystem reside. There are four regions in total, two Secure and two Non-secure regions:

  • 0x4000_0000-0x4000_FFFF which is a Non-secure region.
  • 0x4008_0000-0x400F_FFFF which is a Non-secure region.
  • 0x5000_0000-0x5000_FFFF which is a Secure region.
  • 0x5008_0000-0x500F_FFFF which is a Secure region.

Some peripherals in the base element are aliased to both Secure and Non-secure regions. The final mapping to both the Secure or Non-secure regions, and Privileged or Non-Privileged access support is determined by Peripheral Protection Controllers (PPCs).

Table 3-4 Base peripheral regions

ID (alias) Address Size Region name Description Security
  From To        
1 (10) 0x4000_0000 0x4000_0FFF 4KB TIMER 0 CMSDK Timer. NS-PPC
2 (11) 0x4000_1000 0x4000_1FFF 4KB TIMER 1 CMSDK Timer. NS-PPC
3 (12) 0x4000_2000 0x4000_2FFF 4KB DUAL TIMER CMSDK Dual Timer. NS-PPC
4 (13) 0x4000_3000 0x4000_3FFF 4KB MHU 0 Message Handling Unit 0. NS-PPC
5 (14) 0x4000_4000 0x4000_4FFF 4KB MHU 1 Message Handling Unit 1. NS-PPC
- 0x4000_5000 0x4000_FFFF - - RAZ/WI. -
6 0x4008_0000 0x4008_0FFF 4KB NSPCTRL Non-secure Privilege Control Block. NSP
7 0x4008_1000 0x4008_1FFF 4KB NON-SECURE WATCHDOG Non-secure CMSDK Watchdog. NSP
- 0x4008_2000 0x4008_7FFF - Reserved Reserved. -
8 0x4008_8000 0x4008_BFFF 16KB CryptoCell CryptoCell-312 (if present)a NS
- 0x4008_C000 0x400F_FFFF - Reserved Reserved. -
10 (21) 0x5000_0000 0x5000_0FFF 4KB TIMER 0 CMSDK Timer. S-PPC
11 (22) 0x5000_1000 0x5000_1FFF 4KB TIMER 1 CMSDK Timer. S-PPC
12 (3) 0x5000_2000 0x5000_2FFF 4KB DUAL TIMER CMSDK Dual Timer. S-PPC
13 (4) 0x5000_3000 0x5000_3FFF 4KB MHU 0 Message Handling Unit 0. S-PPC
14 (5) 0x5000_4000 0x5000_4FFF 4KB MHU 1 Message Handling Unit 1. S-PPC
  0x5000_5000 0x5000_FFFF - - RAZ/WI -
15 0x5008_0000 0x5008_0FFF 4KB SPCTRL Secure Privilege Control Block. SP
16 0x5008_1000 0x5008_1FFF 4KB SECURE WATCHDOG Secure CMSDK Watchdog. SP
  0x5008_2000 0x5008_2FFF - Reserved Reserved.  
17 0x5008_3000 0x5008_3FFF 4KB SRAM0MPC SRAM 0 Memory Protection Controller. SP
18 0x5008_4000 0x5008_4FFF 4KB SRAM1MPC SRAM 1 Memory Protection Controller. SP
19 0x5008_5000 0x5008_5FFF 4KB SRAM2MPC SRAM 2 Memory Protection Controller. SP
20 0x5008_6000 0x5008_6FFF 4KB SRAM3MPC SRAM 3 Memory Protection Controller. SP
  0x5008_7000 0x5008_7FFF - - RAZ/WI -
21 (8) 0x5008_8000 0x5008_BFFF 16KB CryptoCell CryptoCell-312 (if present)a S
  0x5008_C000 0x5008_FFFF 4KB - Reserved. -
22 0x5009_0000 0x500F_FFFF 64KB - Reserved. -

Note:

  • For NS_PPC, any Secure access targeting this region is blocked. A PPC controls Non-secure access to this region.
  • For S_PPC, any Non-secure access targeting this region is blocked. A PPC controls Secure access targeting this region.
  • NSP indicates Non-secure privilege access only.
  • SP indicates Secure privilege access only.
  • S indicates Secure access only.
a These regions only exist if the Crypto element is present (when HAS_CRYPTO = 1). Otherwise, these regions are reserved and when accessed they respond with bus error.
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