3.6.2 System information registers

The System Information Register Block provides information on the system configuration and identity. This register block is read-only and accessible by accesses of any security attributes.

This module resides at base address 0x5002_0000 in the Secure region, and 0x4002_0000 in the Non-secure region of the Base Peripheral Region.

Note:

The System information registers block is mapped to both the Secure and Non-secure regions and is visible to both regions without any security protection.

Table 3-63 Summary of System Information Block registers

Offset Name Access Reset value Description Security
0x000 SYS_VERSION RO 0x2204_1743 System Version register All
0x004 SYS_CONFIG RO System configuration dependent System Hardware Configuration register All
0x0100xFCC Reserved - - - -
0xFD0 PIDR4 RO 0x0000_0004 Peripheral ID 4 All
0xFD4 PIDR5 RO 0x0 Reserved -
0xFD8 PIDR6 RO 0x0 Reserved -
0xFDC PIDR7 RO 0x0 Reserved -
0xFE0 PIDR0 RO 0x0000_0058 Peripheral ID 0 All
0xFE4 PIDR1 RO 0x0000_00B8 Peripheral ID 1 All
0xFE8 PIDR2 RO 0x0000_000B Peripheral ID 2 All
0xFEC PIDR3 RO 0x0000_0000 Peripheral ID 3 All
0xFF0 CIDR0 RO 0x0000_000D Component ID 0 All
0xFF4 CIDR1 RO 0x0000_00F0 Component ID 1 All
0xFF8 CIDR2 RO 0x0000_0005 Component ID 2 All
0xFFC CIDR3 RO 0x0000_00B1 Component ID 3 All

SYS_VERSION

The System Version register enables software to read the system part number and revision.

Table 3-64 SYS_VERSION register

Bits Name Access Reset value Description
[31:28] CONFIGURATION RO 0x2 Set to 0x2 for SSE-200 r2.
[27:24] MAJOR_REVISION RO 0x2 Set to 0x2.
[23:20] MINOR_REVISION RO 0x0 Set to 0x0.
[19:12] DESIGNER_ID RO 0x41 Arm Product with designer code 0x41.
[11:0] PART_NUMBER RO 0x743 Part Number for the SSE-200.

SYS_CONFIG

The System Hardware Configuration register enables software to determine the system configuration.

Table 3-65 SYS_CONFIG Register

Bits Name Access Reset value Description
[31:28] CPU1_TYPE RO 0b0010

CPU 1 Core Type:

0b0000 Does not exist.

0b0010 Cortex-M33 core.

Other Reserved.

[27:24] CPU0_TYPE RO 0b0010

CPU 0 Core Type:

0b0000 Does not exist.

0b0010 Cortex-M33 core.

Other Reserved.

[23:20] CPU1_TCM_BANK_NUM RO

0x3 if 4 SRAM banks.

0x2 if 3 SRAM banks.

0x1 if 2 SRAM banks.

Otherwise 0x0.a

SRAM banks that map CPU1 Data TCM.

Number of SRAM banks:

b11 if 4 SRAM banks.

b10 if 3 SRAM banks.

b01 if 2 SRAM banks.

Otherwise b00.

[19:16] CPU0_TCM_BANK_NUM RO 0x0 SRAM banks that map CPU0 Data TCM.
[15:13] Reserved RO 0b000 Reserved.
12 HAS_CRYPTO RO Configuration dependent

CryptoCell Included:

0: No.

1: Yes.

11 Reserved RO 0b0 Reserved.
10 CPU1_HAS_TCM RO ‘1’ if CPU1 exist, otherwise ‘0’. a

CPU 1 has Data TCM:

0: No.

1: Yes.

9 CPU0_HAS_TCM RO 0x0

CPU 0 has Data TCM:

0: No.

1: Yes.

[8:4] SRAM_ADDR_WIDTH RO Configuration dependent

SRAM Bank Address Width.

The size of each SRAM bank is equal to 2 SRAM_ADDR_WIDTH.

Supported values are in the range of:

Minimum of 10: 1KB.

Maximum of 24: 16MB (only if 1 SRAM element exists).

[3:0] SRAM_NUM_BANK RO 0b0100

SRAM Number of Banks:

SSE-200 supports a minimum of 1 for a single processor configuration and 2 for a dual processor configuration.

a These are derived from other system configurations.
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