3.3.4 CPU Local Security Control Register

Each CPU element contains a register block that contains registers to allow the security locks of each processor to be configured. Each register block resides in the same reset and power domain as its associated core. When a processor is powered down, they are also cleared when poweredup.

Table 3-15 CPU Local Security Configuration register map

Offset Register name Access Reset value Full name
0x000 CPUSECCFG RW 0x0 CPU Local Security Configuration register, CPUSECCFG
0x004-0xFC8 - - - Reserved.
0xFD0 PIDR4 RO 0x04 Product ID Register 4.
0xFD4 PIDR5 RO 0x0 Reserved.
0xFD8 PIDR6 RO 0x0 Reserved.
0xFDC PIDR7 RO 0x0 Reserved.
0xFE0 PIDR0 RO 0x59 Product ID Register 0.
0xFE4 PIDR1 RO 0xB8 Product ID Register 1.
0xFE8 PIDR2 RO 0x0B Product ID Register 2.
0xFEC PIDR3 RO 0x00 Product ID Register 3.
0xFF0 CIDR0 RO 0x0D Component ID Register 0.
0xFF4 CIDR1 RO 0xF0 Component ID Register 1.
0xFF8 CIDR2 RO 0x05 Component ID Register 2.
0xFFC CIDR3 RO 0xB1 Component ID Register 3.

CPU Local Security Configuration register, CPUSECCFG

The CPUSECCFG register allows software to set security lock bits at the interface of each associated processor.

Table 3-16 CPUSECCFG register

Bits Name Access Reset value Description
[31:2] - - 0x0 Reserved
[1] LOCKSAU Write one to set. 0 Controls the LOCKSAU signal on the processor. When set to 1, disables writes to the SAU_CTRL, SAU_RNR, SAU_RBAR, and SAU_RLAR registers from software or from a debug agent connected to the processor. When set to 1, it cannot be cleared until reset.
[0] LOCKSVTAIRCR Write one to set. 0 Controls the LOCKSVTAIRCR signal on the processor. When set to 1, disables writes to the VTOR_S, AIRCR.PRIS, and AIRCR.BFHFNMINS registers. When set to 1, it cannot be cleared until reset.
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