A.4.2 Timestamp interface

The following table lists the timestamp interface signals. This timestamp is expected to be driven by a timestamp generator in the expansion subsystem. This input is synchronous to DEBUGSYSCLK and resides in the PD_DEBUG power domain.

Table A-7 Timestamp signals

Signal name Width Direction Clock domain Description
TSVALUEB 64 Input DEBUGSYSCLK Timestamp input value in binary.
Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.