3.7.1 Debug access interface

The Debug access interface of the subsystem provides access to three Access Ports (APs) within the debug subsystem.

The following table lists the debug address map.

Table 3-90 Debug access region interface

Row ID Address Size Region name Description
From To
1 0x0000 0x00FF 256B SYSTEM APB-AP Debug System Access APB-AP.
2 0x0100 0x01FF 256B CPU0 AHB-AP CPU0 Access AHB-AP.
3 0x0200 0x02FF 256B CPU1 AHB-AP CPU1 Access AHB-AP.
4 0x0300 0xFFFF - - Reserved.

The Debug System APB-AP is used to access debug components that are in the debug subsystem, which includes components in the Debug element and components that are connected to the Debug APB Expansion Interface. This AP is only assessable when NIDEN is HIGH.

Note:

A CoreSight™ ROM is also expected at address 0xF008_0000 in your debug expansion logic. This ROM catalogs all CoreSight expansion debug components that are deployed outside the SSE-200 subsystem that are accessible through the Debug APB Expansion Interface.

Table 3-91 System APB-AP address map

Row ID Address   Size Region Name Description
  From To      
1 0x0000_0000 0xEFFF_FFFF - - Reserved.
2 0xF000_0000 0xF000_0FFF 4KB SYSCSROM Debug System CoreSight ROM.
3 0xF000_1000 0xF000_1FFF 4KB SYSFUNNEL Debug System Trace Funnel.
4 0xF000_2000 0xF000_2FFF 4KB SYSCTI Debug System Cross Trigger Interface.
5 0xF000_3000 0xF007_FFFF 500KB - Reserved.
6 0xF008_0000 0xF00F_FFFF 512KB Debug APB Expansion Interface Debug APB Expansion Interface Region.
4 0xF010_0000 0xFFFF_FFFF - - Reserved.

CPU0 AHB-AP is for CPU0 (Primary processor) debug access and also for certification access. It also maps a CoreSight ROM and a Granular Power Requester (GPR).

The accessibility of the access path for the certification is controlled by the CERTDISABLE, CERTDISABLED, CERTREADEN, and CERTREADENABLED control signals.

The following table lists the map for CPU0 AHB-AP, when CERTDISABLED is LOW.

Table 3-92 CPU0 AHB-AP Address Map when CERTDISABLED is LOW

Row ID Address   Size Region name Description
  From To      
1 0x0000_0000 0x2FFF_FFFF   - System memory access by the CPU0 Debug Access Port.
2 0x3000_0000 0x3000_1FFF 8KB CERTMEM Certificate Access Memory region, residing in SRAM0. Write access is allowed and read data is masked to zero if CERTREADENABLED is LOW. Access bypasses the core.
3 0x3000_2000 0xF000_7FFF   - System memory access by the CPU0 Debug Access Port.
2 0xF000_8000 0xF000_8FFF 4KB CPU0CSROM CPU0 Access CoreSight ROM
3 0xF000_9000 0xF000_9FFF 4KB CPU0GPR CPU0 GPR
4 0xF000_A000 0xFFFF_FFFF   - System memory access by the CPU0 Debug Access Port.

The following table lists the map for CPU0 AHB-AP, when CERTDISABLED is HIGH. table.

Table 3-93 CPU0 AHB-AP Address Map when CERTDISABLED is HIGH

Row ID Address   Size Region name Description
  From To      
1 0x0000_0000 0xF000_7FFF   - System memory access by the CPU0 Debug Access Port.
2 0xF000_8000 0xF000_8FFF 4KB CPU0CSROM CPU0 Access CoreSight ROM.
3 0xF000_9000 0xF000_9FFF 4KB CPU0GPR CPU0 GPR
4 0xF000_A000 0xFFFF_FFFF - - System memory access by the CPU0 Debug Access Port.

CPU1 AHB-AP is for CPU1 (Secondary processor) debug access. It also maps a CoreSight ROM and a Granular Power Requester (GPR). The following table lists the memory map for CPU1 AHB-AP.

Table 3-94 CPU1 AHB-AP Address Map

Row ID Address   Size Region name Description
  From To      
1 0x0000_0000 0xF000_7FFF - - System memory access by the CPU1 Debug Access Port.
2 0xF000_8000 0xF000_8FFF 4KB CPU1CSROM CPU1 Access CoreSight ROM
3 0xF000_9000 0xF000_9FFF 4KB CPU1GPR CPU1 GPR
4 0xF000_A000 0xFFFF_FFFF - - System memory access by the CPU1 Debug Access Port.
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