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For each of the output clocks, except for FCLK and SYSCLK, the subsystem provides a Q-Channel interface to allow expansion logic to control the availability of each clock output. These are used to support hierarchical clock gating and are backed up by EXPCLKRDY.
The following list shows the Q-Channel interface for the output clocks, and their signals:
Base element SYSCLK Q-Channel interface for SYSSYSCLK which includes:
Base element FCLK Q-Channel interface for SYSFCLK which includes:
Crypto element SYSCLK Q-Channel interface for CRYPTOSYSCLK which includes:
CPU and Debug element Power Integration Q-Channel interface for CPUDEBUGPIKCLK which includes:
Base, Crypto and System Power Integration Q-Channel interface for BCRYPTOSPIKCLK which includes:
If an interface is not used, then QACTIVE and QDENY signals must be tied LOW and the QREQn output looped back into its QACCEPTn input.
The subsystem does not provide a Q-Channel interface to control DEBUGSYSCLK and DEBUGFCLK. These clocks are controlled by the debug power domain, PD_DEBUG, and as long as the debug power domain is enabled, DEBUGSYSCLK and DEBUGFCLK are active.
The Q-Channel interfaces do not support waking the system from hibernation. To wake from hibernation, you must use the EWC, power control Q-Channel interfaces, or the PDEXPIN inputs.
The following interfaces are each synchronous to the clock that it controls, with only their respective QACTIVE signal being asynchronous:
The following interfaces are asynchronous:
For more details on the Q-Channel protocol, see the AMBA® Low Power Interface Specification Arm® Q-Channel and P-Channel Interfaces.