2.9.3 Processor power domains

Each Cortex®‑M33 processor in the system can have either:

  • A single power domain, PD_CPU<N>CORE, that gates both the core and the debug logic of the processor.
  • Two power domains, with PD_CPU<N>CORE that gates the core, and a separate debug logic power domain, PD_CPU<N>DBG.

The Cortex‑M33 core internally controls, by its Q-Channel, the power state relationship between different power domains of the core. As a result, if SEPARATE_CPUDBG_PD configuration is True indicating that the separate processor debug power domain is supported, then whenever PD_CPU<N>DBG power domain is ON, it requests its Q-Channel interface to turn PD_CPU<N>CORE ON. If a separate processor debug power domain is not supported (when SEPARATE_CPUDBG_PD configuration is False), then both debug and core exist in one power domain. Any attempt to wake the debug logic wakes the core, and any attempt to wake the core also wakes the debug logic.

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