3.3.5 CPU_IDENTITY

The CPU element also implements a CPU_IDENTITY register block that is only visible to accesses on the System interface from the processor within this element.

The base address of this read only register is 0x4001_F000 in a Non-Secure region and 0x5001_F000 in the Secure region and both areas are always accessible. Any writes access to it is ignored. The following table lists the registers in this block.

Table 3-17 CPUSECCFG register

Offset Name Access Reset value Description
0x000 CPUID Read-only CPU<N>_CPUID[3:0] Unique CPU Identity Number, where <N> is ‘0’ for CPU 0 and ‘1’ for CPU 1. Set to zero for a single processor system.
0x004 - 0xFCC Reserved - - -
0xFD0 PIDR4 Read-only 0x0000_0004 Peripheral ID 4
0xFD4 PIDR5 Read-only 0x0000_0000 Reserved
0xFD8 PIDR6 Read-only 0x0000_0000 Reserved
0xFDC PIDR7 Read-only 0x0000_0000 Reserved
0xFE0 PIDR0 Read-only 0x0000_0055 Peripheral ID 0
0xFE4 PIDR1 Read-only 0x0000_00B8 Peripheral ID 1
0xFE8 PIDR2 Read-only 0x0000_000B Peripheral ID 2
0xFEC PIDR3 Read-only 0x0000_0000 Peripheral ID 3
0xFF0 CIDR0 Read-only 0x0000_000D Component ID 0
0xFF4 CIDR1 Read-only 0x0000_00F0 Component ID 1
0xFF8 CIDR2 Read-only 0x0000_0005 Component ID 2
0xFFC CIDR3 Read-only 0x0000_00B1 Component ID 3
Non-ConfidentialPDF file icon PDF version101104_0200_00_en
Copyright © 2016–2018 Arm Limited or its affiliates. All rights reserved.